GB1422150A - Circuit arrangements for digital switching networks - Google Patents

Abstract

1422150 Multiplex pulse Signalling PLESSEY CO Ltd 23 May 1973 [15 Aug 1972] 38058/72 Heading H4L In a time division multiplex digital communication system in which a plurality of a synchronous t.d.m. highways are to be supermultiplexed at an exchange, means are provided for minimizing loss of information due to differences in the local and remote exchange clock frequencies or to loss of synchronism. As shown in Fig. 1, incoming t.d.m. junction J1 is associated with a unit S1 and other incoming junctions J2 &c. are associated with similar units. Each junction accommodates 32 eightbit channels, 30 being used for speech, one for signalling and one for synchronizing. The incoming signals are converted from pseudoternary to binary at BBC and the clock frequency is extracted at CE and various timing signals derived therefrom. The signals from BBC are converted from serial to parallel form at SPC. Signals from SPC are written into the time-switch store RAM under the control of two series of sampling or write-enable localclock pulses A and B respectively, Fig. 3a, which occur in different portions of a bit period, changeover from one series to the other being made when there is a possibility of the edges of an incoming bit clashing with the particular sampling pulse in use. Local clock pulses are generated at LC and include odd-bit timing pulses TBO, even-bit timing pulses TBE, waveform TS which occurs in one-half of the odd and even bits, waveform #TS which occurs in the other half and pulses TF at sixteen times the bit rate. These waveforms are supplied to the bit aligner BA, Fig. 2 (not shown), together with the remote clock waveform #TS<SP>1</SP>. Bit aligner BA measures the phase difference between the sampling pulse in use and the incoming bit edges as by counting pulses TF and when the sampling pulse in use reaches a specified boundary towards each incoming bit edge the bit aligner provides an output of the more suitable pulses A or B. These pulses are supplied to an AND gate G which is enabled if sync. pattern detector SPD indicates that the system is synchronized, to pass the writeenable pulses to RAM. The remote clock waveform #TS<SP>1</SP> is also fed via a divide-by-eight circuit D to a five-bit address counter AC. Each time eight bits are received at SPC they are supplied in parallel form to RAM, the eighth bit also being extracted to enable the address counter AC via path AOCE so that the output of AC is supplied to address multiplexer AM. The current write-enable pulse occurring together with an address from AM causes the eight bit speech sample to be written into memory RAM. A group controller GC controlled by the local clock LC controls the read out from RAM. The group controller is a 256 ten-bit word circulating store serving the random access memories giving access to a superhighway SH. Frame synchronising.-Each time the address counter AC indicates channel 0 (frame sync. channel) via path CO, the eight bits in converter SPC are compared at SPD with a locally generated sync. pulse pattern. If the sync. patterns do not correspond during three successive frames, gate G is blocked and sync. search equipment SSE continuously monitors the incoming bit stream. When the sync. pattern is detected a three-frame count is started and the address counter AC is set to zero via path RS, normal operation being resumed and the search terminated when the sync. pattern is detected during three successive frames.