GB1410094A - Voltage-mode logic circuit - Google Patents

Abstract

1410094 Logic circuits INTERNATIONAL BUSINESS MACHINES CORP 22 May 1973 [22 June 1972] 24318/73 Heading H3T In a voltage mode logic circuit comprising first and second monolithic circuit chips CH1, CH2 interconnected by a line L10 and each having a plurality of interconnected logic circuits LC1-LC5; LC6-LC9, the noise tolerance level and current gain are improved by having an output buffer circuit SC1 on the first chip CH1 with an output impedance lower than the output impedance of the logic circuits and an input buffer circuit RC1 on the second chip CH2 with an input impedance higher than the input impedance of the logic circuits thereon. The output buffer is preferably formed by an emitter follower T3 which also provides a high current gain at its output O2 while translating the signal voltage in a direction towards higher noise tolerance. The input buffer RC1 on the second chip is formed by a diode connected transistor T4. When the inter-chip signal is at a down level, diode T4 is forward-biased as to transmit the down signal to base of a transistor B2 which consequently is cut off and produces an output at the up level. When the inter-chip signal is at the up level, diode T4 is cut-off as to render B2 conducting to produce an output at the down level. Diode T4 isolates the logic circuit LC6 from noise on inter-chip line L10 while providing the required voltage translation. The logic circuits employed may be TTL (as shown) or DTL (Figs. 8A-9B, not shown). The input buffer may be formed by a complementary transistor (Figs. 6B, 9B, not shown). It is also stated that the logic circuits on the first chip are interconnected to form a latch. The Schottky diodes used in the TTL circuits prevent saturation.