GB1392176A - Apparatus for selectively distributing signals - Google Patents

Abstract

1392176 Data processing NATIONAL RESEARCH DEVELOPMENT CORP 26 June 1972 [24 March 1971] 7673/71 Heading G4A [Also in Division H4] A distributer circuit comprises a number of input terminals, each connected to each of a number of logic units. Each logic unit selects one of the inputs and passes it to its one output. The selection is ordered by a combination of signals from a control unit, each logic unit having a respective control unit. The control units each store a series of combinations, providing a series of selections. The circuit may be used for interconnecting digital differential amplifiers (d.d.a.). For example, as shown, there are 64 d.d.a. 101-164, each providing a 2-bit output representing a positive, negative or zero increment. The two leads from each d.d.a. are connected to respective logic units of each of 64 pairs of logic units 301, 301<SP>1</SP>-364, 364<SP>1</SP>. Each pair of logic units is controlled by a respective control unit, e.g. 501, comprising six 8-bit recirculating shift registers. At the end of each interation clock pulses are fed to the control units to provide a sequence of eight 6-bit signals to the respective logic units. Each 6-bit signal causes the output of the corresponding d.d.a. to be passed to the output of the logic unit. Under the control of shift registers 601- 664 units 401-464 the output signals may be reversed, effectively reversing the sign with which they are passed to the d.d.a. Gates 701, 801 &c. are controlled to pass the first of the 8 signals received from the corresponding unit 401-464 to the dx decoder 901-964 and the remaining 7 signals to the dy decoder 901-964<SP>1</SP>. Each decoder provides a positive or negative increment, depending on its input.