GB1391223A - Lagic elements - Google Patents

Lagic elements

Info

Publication number
GB1391223A
GB1391223A GB4680672A GB4680672A GB1391223A GB 1391223 A GB1391223 A GB 1391223A GB 4680672 A GB4680672 A GB 4680672A GB 4680672 A GB4680672 A GB 4680672A GB 1391223 A GB1391223 A GB 1391223A
Authority
GB
United Kingdom
Prior art keywords
type
region
drain
switching transistor
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4680672A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19712150794 external-priority patent/DE2150794C3/en
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB1391223A publication Critical patent/GB1391223A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
  • Logic Circuits (AREA)

Abstract

1391223 Semiconductor devices SIEMENS AG 11 Oct 1972 [12 Oct 1971] 46806/72 Heading H1K A pair of complementary IGFETS, one of which is a switching transistor and the other is a load transistor are produced by forming the switching transistor in a thin semiconductor layer by the double diffusion technique and simultaneously producing the complementary load transistor during the first diffusion stage. The double diffusion technique utilises two diffusions of opposite types through the same aperture to form the source (or drain) region surrounded by the region within which the channel is induced. The device is produced by growing an N-type layer 2 on a high resistivity substrate, e.g. of spinel, opening windows (26, 27, 28), in an oxide layer (25) and diffusing-in an impurity to form one P-type zone (40) for the switching transistor and two further P-type zones (70, 80) for the source and drain of the load transistor. The load transistor diffusion wndows are covered with an insulating layer, e.g. by oxidizing while the remainder is masked with Si3 N4 which is then etched off, and a further window (226) is opened for the drain of the switching transistor. An impurity is diffused-in to form the N<+> type source and drain contact regions 3, 6 of the switching transistor. The masking layers are removed and parts of the semiconductor layer are removed and replaced by growing insulating material to isolate the two transistors. Conductive connections and insulated gate electrodes are then applied. The switching transistor comprises an N<+> type source region 3, a P-type region 4 within which the channel 41'is induced by the gate 19 and a drain region comprising a lightly doped part 5 of the original N-type layer and an N<+> type contact region 6. The load transistor comprises P-type source and drain regions 7, 8 and an N-type region 9 within which the channel 91 is induced by the gate 21. Two such pairs of transistors may be interconnected together with two selector transistor to form a bi-stable storage element in a memory matrix.
GB4680672A 1971-10-12 1972-10-11 Lagic elements Expired GB1391223A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19712150794 DE2150794C3 (en) 1971-10-12 Process for producing an integrated logic circuit and application of the process

Publications (1)

Publication Number Publication Date
GB1391223A true GB1391223A (en) 1975-04-16

Family

ID=5822127

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4680672A Expired GB1391223A (en) 1971-10-12 1972-10-11 Lagic elements

Country Status (7)

Country Link
JP (1) JPS4847777A (en)
BE (1) BE789992A (en)
FR (1) FR2156233B1 (en)
GB (1) GB1391223A (en)
IT (1) IT968836B (en)
LU (1) LU66265A1 (en)
NL (1) NL7213812A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5928993B2 (en) * 1975-03-10 1984-07-17 日本電信電話株式会社 Semiconductor device and its manufacturing method
JPS5227278A (en) * 1975-08-26 1977-03-01 Agency Of Ind Science & Technol Semicondcutor unit
US4087902A (en) * 1976-06-23 1978-05-09 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Field effect transistor and method of construction thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5434179B2 (en) * 1972-07-28 1979-10-25

Also Published As

Publication number Publication date
LU66265A1 (en) 1973-04-13
JPS4847777A (en) 1973-07-06
DE2150794B2 (en) 1976-12-30
FR2156233A1 (en) 1973-05-25
IT968836B (en) 1974-03-20
DE2150794A1 (en) 1973-04-19
BE789992A (en) 1973-04-12
NL7213812A (en) 1973-04-16
FR2156233B1 (en) 1976-08-20

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee