GB1377111A - Delta modulator - Google Patents

Abstract

1377111 Delta-modulation INTERNATIONAL BUSINESS MACHINES CORP 24 Oct 1972 [19 Nov 1971] 49069/72 Heading G4H A delta-modulation encoder is provided with a 4-bit shift register in the feed back loop thereof whereby the bits Nk, N k-1 , N k-2 , N k-3 are stored, Nk being the bit currently transmitted, the storage register thereby holding a 4-bit word which word is used to select firstly a value indicative of the delta step represented by bit Nk which is supplied to the integrator of the feed back loop, and secondly a value of a threshold with which an input is compared to determine the value of the output bit, these values -being worked out empirically but generally being of small magnitude when the word indicates the system is in an "idling state", i.e. the input signal is of near constant amplitude and of larger magnitude when the word consists of, e.g. mostly "1's", indicating that the value of the input is changing rapidly, the system being further provided with a shift register for storing binary coded values V k+3 , V k+2 , V k+1 , V k of samples of the input signal from which a word indicative of the value is derived and used as input to the decoder. As shown, the means 22 is provided for deriving the values F(V) from where they are taken to a subtractor 24 where the difference is derived, the value A k-1 being derived from feed-back loop 20 using the bit stream of the previous k-1 bits and is the total sum of all the incremented steps represented by the transinitted bits. This difference is taken to a comparator 32 where a bit Nk is derived which is "0" or "1" depending upon whether the difference is smaller or greater than a threshold value T. The transmitted bit is also applied to the shift register 28 and the 4-bit word contained therein is applied to a 4-bit-to-1 of 16 converter, not shown, where the 16 output lines form input lines to 2 diode matrices 30, 38 which supply the binary words indicative of the value D, the amount to be added to the integrated value in the summing circuit 26 and equal to the step size represented by N k , and the threshold value T. A receiver, not shown, comprises the same components as feed-back loop 20. The use of the register 28 and the variable step and threshold value devices ensures an absence of overshoot or hunting and provides variable increment encoding with only 1-bit per increment. The use of the device 22 ensures the encoder reacts promptly to changes in V to prevent phase lags in the decoded signal.