GB1376129A - Digital error simulator - Google Patents

Abstract

1376129 Testing data transmission systems POST OFFICE 24 Jan 1972 [26 Jan 1971] 3185/71 Heading H4P A pseudo-random or random pulse generator introduces error bits into a digital data stream. The error bits may be distributed or occur in bunches, at selectable average rates and bunch length. The arrangement provides an error ridden signal for testing a transmission system. TDM 7-bit parallel PCM signals IT1-IT7 are converted into serial form at gate SG10 by gates SG1-SG7 opened by sequential clock pulses SD1-SD7 and pass via an exclusive-OR circuit comprising gates SG14-SG16, the output of which is sampled by strobe pulses from information synch generator (Fig. 1b) at gate SG16 and converted back to parallel form by gates SG32-SG26 and sequential clock SD1-SD7 for storage on bi-stables BT9-BT15. Bi-stables BT16-29 accept the 7-bit signal for transmission on outputs OT1-OT7. A pseudorandom or random pulse generator, having a Zener diode noise generator has its output divided by 2 to generate equal probabilities for the 0 and 1 bits. To insert distributed errors, switches ES1- ES3 are set to position DE, whereby error bits from the error generator, at an average rate selected by divider switch ER, are synchronized with clock pulses PC2 by bi-stable BT23 and are then fed via switch ES to the exclusive-OR gate arrangement SG14-SG16 to modify the clear data bit streams. To insert bunched errors switches ES1-ES3 are set to position BE and a circuit via true and inverted inputs VTT and IVTT supplies pulses of a selectable duration at intervals having a Gaussian distribution (Fig. 2, not shown). Only during the periods of the pulses does AND gate SG11 block the clear data stream and AND gate SG12 admit a bunch of error bits from the error generator. In an alternative arrangement the bunches of errors can be introduced by not inhibiting the data stream but supplying the error bunches to the exclusive-OR gate arrangement as with the distributed errors.