GB1376129A - Digital error simulator - Google Patents
Digital error simulatorInfo
- Publication number
- GB1376129A GB1376129A GB318571A GB318571A GB1376129A GB 1376129 A GB1376129 A GB 1376129A GB 318571 A GB318571 A GB 318571A GB 318571 A GB318571 A GB 318571A GB 1376129 A GB1376129 A GB 1376129A
- Authority
- GB
- United Kingdom
- Prior art keywords
- error
- gate
- generator
- pulses
- errors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
- H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
- H04L1/241—Testing correct operation using pseudo-errors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
1376129 Testing data transmission systems POST OFFICE 24 Jan 1972 [26 Jan 1971] 3185/71 Heading H4P A pseudo-random or random pulse generator introduces error bits into a digital data stream. The error bits may be distributed or occur in bunches, at selectable average rates and bunch length. The arrangement provides an error ridden signal for testing a transmission system. TDM 7-bit parallel PCM signals IT1-IT7 are converted into serial form at gate SG10 by gates SG1-SG7 opened by sequential clock pulses SD1-SD7 and pass via an exclusive-OR circuit comprising gates SG14-SG16, the output of which is sampled by strobe pulses from information synch generator (Fig. 1b) at gate SG16 and converted back to parallel form by gates SG32-SG26 and sequential clock SD1-SD7 for storage on bi-stables BT9-BT15. Bi-stables BT16-29 accept the 7-bit signal for transmission on outputs OT1-OT7. A pseudorandom or random pulse generator, having a Zener diode noise generator has its output divided by 2 to generate equal probabilities for the 0 and 1 bits. To insert distributed errors, switches ES1- ES3 are set to position DE, whereby error bits from the error generator, at an average rate selected by divider switch ER, are synchronized with clock pulses PC2 by bi-stable BT23 and are then fed via switch ES to the exclusive-OR gate arrangement SG14-SG16 to modify the clear data bit streams. To insert bunched errors switches ES1-ES3 are set to position BE and a circuit via true and inverted inputs VTT and IVTT supplies pulses of a selectable duration at intervals having a Gaussian distribution (Fig. 2, not shown). Only during the periods of the pulses does AND gate SG11 block the clear data stream and AND gate SG12 admit a bunch of error bits from the error generator. In an alternative arrangement the bunches of errors can be introduced by not inhibiting the data stream but supplying the error bunches to the exclusive-OR gate arrangement as with the distributed errors.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB318571A GB1376129A (en) | 1972-01-24 | 1972-01-24 | Digital error simulator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB318571A GB1376129A (en) | 1972-01-24 | 1972-01-24 | Digital error simulator |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1376129A true GB1376129A (en) | 1974-12-04 |
Family
ID=9753540
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB318571A Expired GB1376129A (en) | 1972-01-24 | 1972-01-24 | Digital error simulator |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1376129A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0044098A1 (en) * | 1980-07-14 | 1982-01-20 | Staat der Nederlanden (Staatsbedrijf der Posterijen, Telegrafie en Telefonie) | System for testing a modem |
-
1972
- 1972-01-24 GB GB318571A patent/GB1376129A/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0044098A1 (en) * | 1980-07-14 | 1982-01-20 | Staat der Nederlanden (Staatsbedrijf der Posterijen, Telegrafie en Telefonie) | System for testing a modem |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA1169946A (en) | Process and apparatus for synchronization of digital signals | |
US3659046A (en) | Message scrambler for pcm communication system | |
ES8800551A1 (en) | High-speed digital loop transceiver. | |
GB1264814A (en) | ||
JPS5639694A (en) | Method and device for synchrnonizing timing in transmission of digital information signal | |
GB1285976A (en) | Diversity switching for digital transmission | |
GB1410637A (en) | Bit timing regeneration | |
GB1492134A (en) | Method of measuring the bit error rate of a regenerated pcm transmission path | |
US3057962A (en) | Synchronization of pulse communication systems | |
GB1344351A (en) | Digital information detecting apparatus | |
GB1434050A (en) | Electric power system supervisory control system comprising a/d converters at various points of the power system | |
FR2245957B1 (en) | ||
GB1216352A (en) | Improvements in or relating to echo suppression systems | |
GB1376129A (en) | Digital error simulator | |
GB1190904A (en) | Digital Data Receiver | |
GB1439579A (en) | Digital speech detector | |
GB1421568A (en) | Supervision arrangement for a pulse code-modulation system | |
GB1471984A (en) | Apparatus for supervising operation of a multiplex system | |
GB1280827A (en) | Improvements relating to apparatus for synchronizing a clock with a received signal | |
GB1256371A (en) | Scrambling arrangement for sampled-data time-allocation communication systems | |
GB1312550A (en) | System for the transmission of information at very low signal- to-noise ratios | |
GB1512086A (en) | Pcm transmission system | |
GB1265402A (en) | ||
GB1176510A (en) | Improvements in or relating to electrical time division communication systems | |
ES371682A1 (en) | Frame synchronization arrangement for pcm systems |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PLNP | Patent lapsed through nonpayment of renewal fees |