GB1373395A - Pulse code modulation encoder - Google Patents

Abstract

1373395 Analogue to digital converters PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 13 Oct 1971 [15 Oct 1970] 47646/71 Heading G4H In a dual ramp analogue to digital converter the input analogue signal is integrated whilst binary weighted clock pulses are counted, the integration being stopped that the next clock pulse after the integrator voltage exceeds a threshold level, the integrator then being discharged to zero whilst equi-weighted clock pulses are counted. The first and second counts provide fine and coarse digital components of the analogue signal. Alternatively a non-linear integrator may be used in conjunction with equal spaced, instead of binary weighted, clock pulses. In Fig. 7 an analogue signal from a microphone 700 is sampled by brief closure of switch 702 and the sample is integrated in a Miller integrator 705-708, whilst binary weighted clock pulses are fed to counter 722 by a switch 723. After the integrator voltage reaches a threshold voltage plus Eh, of unit 709 or minus Eh of unit 711, signal C or C3 from the units by AND gate 726 at the next binary weighted clock pulse causes the integrator to integrate down to zero by opening switch 703 and closing switch 712 or 713 to supply positive or negative reference voltage to the integrator. During discharge of the integrator equi-spaced clock pulses tn are fed via switch 733 to a binary counter 732. The coarse and fine digital components are combined in a logic unit (not shown). The binary counter 732 may have an extra position LO so that if the threshold unit only responded some way past its proper threshold value causing the integrator to proceed to a timing instance one later than it should have, a longer period can be accommodated in counter 732 and a carry is added into the least significant position of the coarse digital component in counter 722.