GB1334530A - Sampling arrangement for use in electromechanical recording apparatus - Google Patents

Abstract

1334530 Sampling circuit for graphical recorders MAGYAR TUDOMANYOS AKADEMIA KUTATASI ESZKOZOKET KIVITELEZO VALLALATA 9 Nov 1970 [13 Nov 1969] 53265/70 Headings G1J and G1U In order to display a cyclically recurring waveform such as A, Fig. 2, on a graphical recorder having insufficient bandwidth, the waveform is sampled repeatedly once during each cycle, at a sequence of points encircled in Fig. 2 - progressively advancing within each cycle, so that by displaying the successive samples graphically the form of the waveform will eventually be apparent. As described the input waveform A, Fig. 2 is applied to a square 1, Fig. 1, and pulse generator 2, to produce sync pulses B at the positive-going zero cross-overs. These are applied, via a normally open gate 3 to set a trigger 4. The output voltage D from trigger 4 is integrated R 1 C 1 , producing an exponentially rising voltage E which is compared 7 with a second, more slowly rising, exponential voltage F from a second integrator R 2 C 2 . When the two voltages E and F are equal a pulse generator 8 produces a pulse G which (i) opens a gate 5 thereby allowing a sample of the waveform A to pass to a recorder 6, (ii) resets trigger 4, and (iii) causes a circuit 9 to discharge capacitor C1, gate 3 being closed while this is being done. This process repeats until the sampling pulse G has processed through a complete cycle of the waveform A, whereupon, at the end of a cycle capacitor C 2 is dishcarge by a circuit 10 and the whole sequence is repeated. Three circuits are outlined for controlling the discharge circuit 10 to ensure that its operation is properly synchronized with the end of a cycle of the waveform A. In the first, Fig. 3 (not shown), circuit 10 is activated when a sampling pulse G coincides with a sync pulse B, in the second, Fig. 4 (not shown) for greater accuracy, circuit 10 is activated when the integral of the output voltage D of the trigger 4 rises to a reference level, and in the third, Fig. 5 (not shown) the second circuit is modified by differentiating the integrated output voltage D from the trigger 4, storing the result on a capacitor (C4) and using it to set a constant charging current (16) for a second capacitor (C5), and comparing (17) the voltage across the second capacitor with a reference voltage.