GB1328531A - Pulse generator circuits - Google Patents

Abstract

1328531 PUT pulse generator circuits AMF Inc 19 Jan 1971 [27 Jan 1970] 3845/70 Heading H3T A pulse generator includes a first resistor R1 connected in series with a diode D1 across supply terminals 1, 2, a capacitor C1 connected between the anode of a programmable unijunction transistor PUT and the junction of R1 and D1, a second resistor R2 connected between the anode of the PUT and one of a pair of load output terminals, third and fourth resistors R3, R4 the gate of the PUT being connected to the junction of R3 and R4 and a transistor VT1 having its base connected to the cathode of the PUT, its emitter connected to the supply and its collector connected to the one output terminal thereby providing an output pulse train of predetermined period and mark/space ratio. Capacitor C1 charges via relay RL1, resistor R2 and diode D1 until the voltage at the anode A of the PUT is sufficient to turn the PUT on. Transistor VT1 now conducts and the capacitor C1 starts to discharge via resistor R1, the PUT and the base-emitter path of transistor VT1. Diode D1 is made non-conductive due to the drop in potential at the negative side of the capacitor C1. When the voltage across the capacitor C1 has fallen to a certain value diode D1 conducts again and shunts current from C1 and the PUT so that the PUT and the transistor VT1 turn off. The cycle then restarts with the capacitor C1 recharging. In a cycling time delay relay having variable on/off times (Fig. 2, not shown) a transistor (VT2) is added between the capacitor C1 and the anode of the PUT to provide amplification for the discharge current and enabling longer times by increasing the value of R1. An audio generator may be obtained by replacing relay RL1 by a loud speaker (L, Fig. 3, not shown). The period can be adjusted by changing the values of C1, R1 and R2 and the mark/space ratio is dependent on the values of R1, R2. The voltage required across C1 to trigger the PUT is set by the voltage applied to the anode gate G from resistor divider R3, R4 and stability of the timing V supply voltage and temperature characteristics is obtained.