GB1315749A - Demodulator for binary coded words - Google Patents

Abstract

1315749 Digital to analogue converters KRONE KG 19 April 1971 [9 March 1970] 23560/71 Heading G4H A circuit for decoding binary coded words in a P.C.M. system comprises a store 100 for receiving the incoming words, a first decoder D1 connected to the store and adapted to receive m most significant bits and n least significant bits of each word, a second decoder D2 adapted to receive the m bits from the store and weighted resistors KD1-RD7 connected to switches S1-S7 actuated by the output of the second decoder. The most significant bit of each word is a polarity bit which controls a switch BS 6 of the decoder D1, shown in detail in Fig. 4a, to supply a positive or negative reference voltage to a parallel arrangement of binary weighted resistors RB1-RB6. The resistors RB1-RB4 are connected in circuit by switches BS1-BS4 actuated by the n bits to select the particular one of the sixteen subdivisions (for n=4) of the amplitude band determined by the m bits. To remove the ambiguity due to the first two bands of the expansion characteristic having the same slope, the m bits are fed to an OR gate 111 which actuates a switch BS5 if any of these bits has a logical value "1". The output voltage from the parallel resistor network is fed via an inverting amplifier V to a potentiometer formed by the weighted resistors RD1-RD7. The decoder D2 comprises seven NAND gates which control the switches S1-S7 to multiply the output U A <SP>1</SP> of the decoder D1 by a factor which determines the amplitude band of the analogue output signal. The switches may be field effect transistors. In a modification the output from the resistor network RB1-RB6 is fed through a second inverting amplifier when the polarity bit changes over ganged switches connected to the outputs of the amplifiers. A ladder network replaces the network RB1-RB6 in a further modification.