DE2011056B2 - PULSE CODE DEMODULATOR WITH EXTENSION CHARACTERISTICS KINKING CHARACTERISTICS - Google Patents

Description

The invention relates to a pulse code demodulator for decoding digital signals of an (n + m + I) -bit code into analog signals with a stretching characteristic exhibiting kink characteristic, which consists of 2 ^{(m + 1)} linear sections, each comprising 2 "amplitude levels, consisting of one second decoder for m bits, a first decoder and an amplitude reverse converter, which has a voltage divider made up of damping resistors, the resistance value of which is determined according to the kink characteristic, and a number of switches connected to the connection points of adjacent damping resistors, the first decoder having one end of the Voltage divider feeds, while the switches can be controlled by the second decoder.

By means of such a known pulse code demodulator (cf. German Auslegeschrift 1 276 708, in particular FIG. 7), digital signals are recoded into analog signals that had previously been converted into digital signals in a pulse code modulator. The pulse code modulator has an amplitude converter which has a Presser characteristic with a kink characteristic, which consists of 2 ^{(m + 1)} linear sections, each comprising 2 " amplitude levels. The m-bit combination then gives the position of the analog signal in question in one of the linear sections, the 1-bit the sign and finally the n-bit combination the associated amplitude level.

The pulse code demodulator then also uses the amplitude converter Change in the dynamics of the analog signals caused by Presser characteristics reversed, in that the amplitude converter has a stretching characteristic.

This pulse code demodulator also has a third decoder for the sign bit, which is one of the amplitude reverse converters downstream pole reverser controls. The polarity reverser thus takes a polarity reversal if necessary the output voltage of the amplitude reconverter when the output voltage reaches its magnitude after is certain. This has the disadvantage that, when reversing the polarity, very small voltages, such as those encountered, for. B. at an 8 (and more) -bit decoding at the output of the pulse code demodulator, absolute errors of the Umpolers enter the decoded signal with their entire size.

In this known pulse code demodulator, the connection points of the damping resistors Pre-currents of different sizes are fed in according to the kink characteristic to be generated. aside from that the switches each connect two adjacent connection points of the damping resistors.

Since in the known pulse code demodulator (2 " ¹ " ¹ ) there are current sources for the bias currents, which must also be precisely adjustable, this means a considerable technical effort, in particular. special for a z. B. 8-bit code word to be decoded according to the 13-segment compander characteristic, where m = 3. -

The switches must also be designed as so-called "floating" switches, the two adjacent ones Connection points of the voltage divider formed by the damping resistors, their potentials can be different (i.e. swim), short-circuit or disconnect from each other. Such Switches are technically difficult to implement.

Closing the switches, an ideal switching behavior show d. In other words, in the closed position, its resistance must be zero, in the open position, however, it must their blocking resistance will be infinite. The behavior of the switches that is not ideal falsifies that at the output of the pulse code demodulator potential to be tapped.

In summary, it should be noted that this known pulse code demodulator due to the large technical effort and the possible sources of error not for the decoding of digital code words with a higher number of bits, such as 8 bits, is suitable.

Avoiding these difficulties and disadvantages is the task of the inventive pulse code demodulator of the type mentioned. It is characterized in that the first decoder is designed for (n + 1) bits and has an addition / decoder switch that can be actuated depending on the value of the sign bit, by means of which from the second linear section of the kink characteristic a positive or negative constant voltage can be added to the output voltage of the first decoder, and that the switches in the closed position connect their associated connection points of adjacent damping resistors to the output of the pulse code demodulator. |

Since the first decoder is designed for (n + 1) bits - = *, it also decodes the sign bit so that the polarity is reversed from the damping resistors before the voltage divider, i.e. at a point where there are still large voltage amplitudes appear. In this way, the absolute error that occurs when the polarity is reversed is divided down by the voltage divider as a function of the voltage divider ratio.

The voltage divider provided for the amplitude reverse converter in the pulse code demodulator according to the invention differs from the known voltage divider fundamentally in that each connection point of the voltage divider can be connected to the converter output, while with the known Amplitude converter the output voltage of the converter is always tapped at the same point will. This has the advantage that no damping resistors have to be bridged and no power sources for pre-currents are necessary. This allows the voltage divider of the amplitude I back converter of the pulse code demodulator according to the invention are carried out very precisely, which is why the accuracy that can be achieved with demodulation is very high.

A preferred embodiment of the pulse code demodulator according to the invention is that the first decoder has a network of evaluation resistors, which are followed by an operational amplifier connected as a summation amplifier and a decoding switch is connected upstream, and that the decoding switch can be actuated by one of the η bits each to adjust the relevant evaluation resistor to be connected to a sign bit decoding switch, through which a positive or negative reference voltage can be supplied depending on the sign bit.

It is also useful that the addition-decoding switch on the one hand to the sign bit decoding switch and on the other hand via an addition evaluation resistor to the operational amplifier connected.

This has the advantage that the constant voltages are obtained from the reference voltages, that is no additional voltage sources are required.

This embodiment can be improved by adding the decoding switches and the addition-decoding switch are connected to a single reference voltage that to the output of the operational amplifier a second operational amplifier is connected in inverter circuit and that the outputs of the two operational amplifiers each have a sign bit selection switch that can be actuated depending on the sign bit are connected to a second impedance converter.

In this way, only a single reference voltage is required, so that all decoding switches only need to switch a polarity and can therefore have a simpler structure. The second impedance converter is desirable to increase the on resistance of the sign bit select switch To be able to neglect, since commercially available impedance converters have an input resistance of more have as 1 GO.

A further simplification results from the fact that instead of the evaluation resistors and the Addition evaluation resistor a ladder is provided and that the one sign bit selection switch is directly connected to the output of the chain conductor.

By replacing all evaluation resistors with the ladder, one saves one of the operational amplifiers because of the high input resistance of the second impedance converter.

The invention can also be advantageously developed in that one pole of the switch is connected to a first impedance converter.

In this case, the size of the on-resistance of the switches is irrelevant, since the input resistance of a commercially available impedance converter can be over 1 Gü. The potentials at the connection points of the voltage divider cannot be falsified by additional currents.

If the pulse code modulator according to the invention is used for time division multiplex systems, the first impedance converters also serve as charging amplifiers for storage capacities.

The invention is explained in more detail with reference to the drawing. It shows

F i g. 1 a 13-segment compander curve,

F i g. 2 the structure of a code word to be decoded,

F i g. 3 shows the basic circuit diagram of an exemplary embodiment of the pulse code demodulator according to the invention,

F i g. 4a, 4b and 4c show the basic circuit diagram of a first, second and third exemplary embodiment of a first decoder of FIG. 3,

F i g. 5 the output voltage at the first decoder and at the pulse code demodulator for different code words,

F i g. 5 a and 5 b show the relationship between analog and digital signals in the vicinity of the zero point in the pulse code modulator or pulse code demodulator,

F i g. 6 is a table for a better understanding of FIG. 5 and

F i g. 7 shows an embodiment of a second decoder of FIG. 3.

The pulse code demodulator according to the invention not only enables simple decoding of the in it is fed digital signals or code words into analog signals made by decoders, but rather before the decoding is complete

Modification of the dynamics of the analog signals achieved by means of an amplitude converter.

For the illustrative embodiment of the pulse code demodulator according to the invention are as special kink curve a 13-segment compander curve (see COM XV, question 33 temp. doc. no. 34 from September 25 to October 6, 1967, published by the CCITT) of the amplitude reverse converter and an 8-bit decoding accepted.

On the abscissa of the coordinate system of FIG. 1, code words combined in groups I to VIII are plotted (for the positive part), while the ordinate denotes the output signal U _{A of} the amplitude reverse converter and thus of the pulse code demodulator.

The compander curve is designed here as a kink curve, ie it consists of a number of linear sections. If the number of these sections is given generally as 2 ^{(m + 1)} , m = 3 results for our exemplary embodiment, since there are 16 linear sections. Each (positive) linear section is assigned one of the code word groups (I to VIII) on the abscissa, each of which consists of 2 ″ code words (not shown in FIG. 1).

This corresponds to 2 "amplitude levels of each linear section of the kink characteristic. For the exemplary embodiment under consideration, η = 4 is set so that a total of 16 code words are available for each code word group of the origin of coordinates together have their own section, so that there are only 6 + 6 + 1 = 13 linear sections (or segments), the slope of which differs by a factor of 2. The law of formation of the slope is retained in our case.)

The (3 + 1) -bit combination thus indicates which code word group and thus which linear one The code word in question belongs to the section of the kink curve, while the 4-bit combination then includes the Position within the code word group and thus within the linear section, i.e. its amplitude level, certainly.

In our case, a digital word to be coded has the structure of Fig. 2.

According to FIG. 3, the inventive pulse code demodulator has a second decoder D ₂ for m bits and a first decoder D ₁ for basically (n + 1) bits, and the first decoder D ₁ applies an output voltage U _A to a series circuit of damping resistors RD ₁ to RD ₁ that form a voltage divider.

The damping _{resistors, RD 1} to RD _n have different resistance values, as shown in FIG. 3 it can be seen to the linear sections of the buckling curve of F i g. 1, which will be explained in more detail. R denotes a unit resistance value.
Each connection point of the damping resistors RD ₁ to RD ₁ can be connected to the input of an impedance converter IW via an associated switch S ₁ to S ₇ . The switches S ₁ to S ₇ can be operated by the second decoder D ₂ .

In Fig. FIG. 4a is a first embodiment of the first decoder D ₁ of FIG. 2 shown in more detail. Depending on the value of the sign bit (see Fig. 2), a sign bit decoding switch S%

be actuated to create a downstream network of a sign bit evaluation resistor RB ₆ , an addition evaluation resistor RB ₅ and evaluation resistors RB ₁ to RB ₄ . to be connected to a positive reference voltage + U _ref or a negative reference voltage - U _ref .

The evaluation resistors RB ₁ to RB ₄ . have binary graded resistance values, as shown in Fig. 4a can be seen in order to determine the individual amplitude levels within the linear sections of the buckling curve of FIG. 1, which will be explained in more detail. R * denotes another unit resistance value.

If at least one of the m bits (see FIG. 2) is a logical "1", an OR gate OJ? the addition / decoding switch Sf is closed and thus the addition evaluation resistor RB ₅ has + U _ref or - U _ref applied. Likewise, one or more of the decoding switches S% to S% are closed when one or more bits of the n-bit combination (see FIG. 2) are a logical "1" (or "! * <), In which If the corresponding downstream evaluation resistors RB ₁ to RjB _{4 are} also acted upon with + U _ref or - U _ref.

In the case of the first decoder D _{1, the} m-bit combination is only significant if there is a transition from an OOO word to a word with at least one “1” among the m bits during operation. The first decoder D ₁ is therefore to be regarded as being designed in principle for (n + 1) bits.

An operational amplifier V with a feedback resistor R _{RK is} connected to the output of the network of the evaluation resistors RiJ ₁ to RB ₆ , so that the operational amplifier V operates as a summation amplifier. The voltage arises at its output

ref

RK

RB;

The summation is carried out over all resistors RB ₁ that are connected to the reference voltage + U _ref or - U _ref .

An advantageous development of the in FIG. 4a illustrated embodiment of the first decoder D ₁ is in FIG. 4b, with matching components having the same reference numerals as in FIG. 4a are designated.

A comparison of FIG. 4b with 4a shows directly that the switch Sf of FIG. 4a, by means of which a positive reference voltage + U _ref or a negative reference _{voltage -U ref} can be applied, has been omitted. Instead, the circuit manages with a single reference voltage + U _ref , so that the decoding switches Sf to Sf only need to switch one polarity, which simplifies their structure.

A first operational amplifier V ₁ connected as a summation amplifier , which corresponds to the operational amplifier V of FIG. 4a, therefore always shows a negative voltage - U _A at its output. The voltage - U _A is inverted by a second operational amplifier V ₂ connected as an inverter with resistors R _V2 (compare, for example, Ti et ze and Schenk, semiconductor circuit technology, Springer-Verlag, 1969). '

The output of the first and second operational amplifier V ₁ and V ₂ is followed by a sign bit selector switch S _Vl and Sy ₂ , one of the two selector switches being actuated depending on the value of the sign bit to set the positive voltage U _Ä or the negative voltage - U _A to a second impedance converter JWi leading to the voltage divider from the damping resistors RD ₁ to RD _1. The second impedance converter IW ₁ is useful in order to make the through resistance of the switches Sy ₁ and Sy ₂ negligible, since commercially available impedance converters have an input resistance of more than 1 GO.

In the exemplary embodiment of the first decoder D 1 from FIG. _{1 is used.} 4b, instead of the evaluation resistors RB ₁ to RB _6, a ladder of resistors R ** and 2R ** (cf. FIG. 4c), then one of the operational amplifiers can be saved because of the high input resistance of the second impedance converter IW _1. Switches S_ and S ₊ correspond to switches Sy ₁ and Sy ₂ , while the remaining operational amplifier is denoted by% and analogous to V ₂ of FIG. 4b is connected as an inverter.

The voltage U% occurring at the output of the chain conductor is determined as follows (David F. Hoeschele, Analog-to-Digital / Digital-to-Analog Conversion Techniques, p. 108ff.):

UT = 4-

U _n

ef

'32 ⁵ '64; R ** + R _L

with D ₁ = state of the bits controlling the decoding switch Sf and R _L = resistance value of the ladder load resistor R _L , which is also the input resistance of the operational amplifier % .

If one of the resistors 2 R ** in F i g. 4c to ground via the assigned switches Sf , ie 0 V, then D ₁ = 0 must be set, in the other case D _; = 1. If R _L = 2 R ** is selected, only two resistance values (R **, 2R **) are necessary for this exemplary embodiment of the decoder D _1.

In Fig. 5, the output voltage U _{A of} the first decoder D _{1 is recorded} over all possible code words with positive voltage values, with

Code words with the same m-bit combination on jj of the abscissa corresponding to F i g. 1 the code word groups Form I to VIII.

In Fig. 6 you can see the exact assignment between code word groups I to VIII and the m-bit combination (where the logical "1" as "Ii" is shown).

For code words with corresponding negative voltage values, the characteristic curve of F i g. 5 Think zero point symmetrically downwards, since these code words are symmetrical to the abscissa and differ only in the sign bit.

In Fig. The combination of the η bits of the code word and constant sign bit (namely, L or 1) corresponding to the output voltage of the decoder D ₁ in 16 stages from: 5 mBits increases, starting from the zero point while maintaining combination (000 namely according to Fig. 6) tension

UU -

DlS "^

ref

as can be seen from the above formula for U _A. The beginning of this step-shaped output voltage of the decoder D ₁ can be seen in more detail in FIG. 5b. The height of a voltage level is therefore

U _A = U " _f

γ, (= 1 LSB (least significant bit)).

It can also be seen that the sign bit evaluation resistor RB ₆ with the resistance value 32 R leads, depending on the sign bit, to an addition of + or - \ ISB (cf. also FIG. 5b).

This is necessary in order to avoid the so-called quantization error when the co-

of the decoder and the decoder ± ^ LSB .

Up to now the case of code word group I was considered, in which all m bits are "0" (see also FIG. 6). If, on the other hand, at least one of the m bits is a logical "1", the decoding switch S * is closed because of the OR element OR (see FIG. 4), so that the addition evaluation resistor RB ₅ , with the resistance value R * According to the formula given above, with otherwise the same combination of the η bits, the voltage

_rr . R * ß _ U _n ,

R *

3 °

Claims (7)

Claims: 35 is added. For this reason, the output voltages of the decoder D1 for the code word groups II to VIII are identical if these code words match with the same sign bit in the n-bit combination. The second decoder D2 and the voltage divider formed by the damping resistors RD1 to RD1 serve to convert the output voltage UA of the decoder D1 into the required kink characteristic (see FIGS. 1 and 5). The 13-segment compander characteristic of FIG. 1, which is a special form of the knee curve for decoding 8-bit PCM signals for the 30/32 channel PCM system, has the property that the voltage changes by a factor of 2 from knee to knee. This is why the voltage divider is binary (R, 2R, 4R, SR, 16R, 32R). The decoder D2 closes one of the switches S1 to S7 as a function of the combination of the m bits (see FIG. 6). The second decoder D2 can for example be the one shown in FIG. 7 have indicated structure, where NAND gates can be seen, which are each connected to one of the switches S1 to S7. When a logical "0" occurs at the output of one of the ISMiVD elements, the associated switch is closed. 55 1. Pulse code demodulator for decoding digital signals of an (n + m + 1) -bit code into analog signals with a stretching characteristic exhibiting kink characteristic, which consists of 2 ⁽ '" ⁺¹⁾ linear sections, each comprising 2" amplitude levels, consisting of a second Decoder for m bits, a first decoder and an amplitude reverse converter, which has a voltage divider from damping resistors, their resistance value is determined in accordance with the kink characteristic, and has a number of switches connected to the connection points of adjacent damping resistors, the first decoder feeding one end of the voltage divider, while the switches can be controlled by the second decoder, characterized in that the first decoder (D ₁ ) is designed for (n + 1) bits and has an addition-decoding switch (Sf) that can be actuated as a function of the value of the sign bit, by means of which from the second linear section (via II in FIG. 1) of the kink characteristic curve a positive or negative constant voltage can be added to the output voltage of the first decoder, and that the switches (S ₁ to S ₇ ) in the closed position connect their associated connection points of adjacent damping resistors (RD ₁ to RD ₁ ) to the output of the pulse code demodulator (Fig. 3) . 2. Pulse code demodulator according to claim 1, characterized in that the first decoder (D ₁ ) has a network of evaluation resistors (RB ₁ to RB ₄ ) , which are followed by an operational amplifier (V) connected as a summation amplifier and in each case a decoding _{switch (S 1} * to S $) , and that the decoding switches (S ₁ * to S |) can each be actuated by one of the η bits in order to connect the relevant evaluation resistor to a sign bit decoding switch (S *) through which, depending on the sign bit, a positive (+ U _ref ) or negative (- U _re f) reference voltage can be supplied (FIG. 4a). 3. Pulse code demodulator according to claim 2, characterized in that the addition-decoding switch (S *) on the one hand to the sign bit decoding switch (S *) and on the other hand via an addition - evaluation resistor (RB ₅ ) is connected to the operational amplifier (V) (F i g.4a). 4. Pulse code demodulator according to claim 3, characterized in that the decoding switch (S ₁ * to Sf) and the addition-decoding switch (S *) are connected to a single reference voltage (+ U _ref ) that to the output of the operational amplifier (X) a second operational amplifier (] ζ) is connected in the inverter circuit and that the outputs of the two operational amplifiers are each connected via an operable in dependence on the sign bit sign bit selector switch (S _Vv S _Vo) with a second impedance converter (IV [Q (F i g. 4b). 5. Pulse code demodulator according to claim 4, characterized in that instead of the evaluation resistors and the addition evaluation resistor a ladder (R **, 2 R **) is provided and that the one sign bit selector switch (S ₊ ) directly to the output of the Chain conductor is connected (F i g. 4c). 6. Pulse code demodulator according to one of the preceding claims, characterized in that one pole of the switches (S ₁ to S ₇ ) is connected to a first impedance converter (/ W ^. 7. Pulse code demodulator for time-division multiplex systems according to claim 6, characterized in that the first impedance converter (IW) also serves as a charging amplifier for storage capacities. For this purpose 2 sheets of drawings 109551/440