GB1307451A - Information transmission synchronization systems - Google Patents

Abstract

1307451 Digital transmission; frame synchronizing MULLARD Ltd 10 June 1971 19911/71 Heading H4P Frame synchronization of a system also having bit synchronization is performed by generating a defined sequence of bits, at one rate, which on reception are stored and compared with an identical sequence generated in one bit time, correct correlation of the whole or a determined part of the two sequences providing a frame sync. signal. The sequence may be generated in pseudo-random manner and comprise 31 bits. Bit synchronization at the receiver is effected by a phase lock loop arrangement. At the transmitter, Fig. 1, 2 khz clock pulses CH2 are passed to a biphase modulator MOD, pseudo random generator PRBS and to AND gate A1. A<SP>1</SP>O<SP>1</SP> signal on start lead ST triggers monostable circuit MS1 enabling A1 for this period allowing clock pulses through OR gate to be transmitted, and at the receiver are used to lock the oscillator providing bit synchronization. The pulse trailing edge from MS1 fires monostable circuit MS2 enabling AND gate A2 and operates circuit PS setting PRBS to the "all 1's" state hence starting the generated sequence at a determined point. The output from PRBS is transmitted in ternary form during the unstable time of MS2. At the receiver Fig. 3 64 khz clock pulses generated preferably by division from a 128 khz oscillator drives a similar generator PRBS through a 31 bit sequence in 1 bit time, also starting at an "all 1's" state, which is supplied to a correlator CO also receiving a sequence already stored in the circulating shift register SR. If a determined number of identities are found a frame sync. signal FSS is derived from register REG via AND gate A3 enabled by clock pulses STR at bit rate. Frame synchronization is initiated by a data select signal being transmitted which when received in data select unit DS switches over shift register SR to circulatory mode.