GB1265014A - - Google Patents
Info
- Publication number
- GB1265014A GB1265014A GB1265014DA GB1265014A GB 1265014 A GB1265014 A GB 1265014A GB 1265014D A GB1265014D A GB 1265014DA GB 1265014 A GB1265014 A GB 1265014A
- Authority
- GB
- United Kingdom
- Prior art keywords
- pair
- arrays
- shift register
- configuration
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
Landscapes
- Advance Control (AREA)
- Hardware Redundancy (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
1,265,014. Data storage. INTERNATIONAL BUSINESS MACHINES CORP. 22 Oct., 1969, No. 51786/69. Heading G4C. A digital data storage system comprises duplexed storage arrays 1A, 1B, a configuration shift register 15, and control means arranged selectively to render either or both storage arrays active or inactive in accordance with the contents of the configuration register. Fig. 1 shows two pairs of associative storage arrays 1A, 1B, and 2A, 2B, each pair as in Specification 1,265,013 which is referred to. Each array has a column of selector triggers, one trigger e.g. 10A or 10B per word location, the triggers of a given array being connected as a shift register so that their states can be shifted down one by a " next " operation. Each pair of arrays has a 2-bit configuration shift register 15 or 16 feeding both columns of selector triggers in common, the output of these columns of the first pair of arrays feeding the shift register 16 of the second pair. Input/output registers 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B link the arrays to buses 3, 4 as shown. The arrays of a given pair store identical data. Corresponding input/ output registers are continually compared, as are corresponding selector triggers, inequality producing an error indication. If a configuration control line 18 is not energized and both stages of configuration shift register 15 or 16 are " zero," the corresponding pair of arrays is isolated from the rest of the system and the connections between the configuration shift registers by-pass the columns of selector triggers in this pair of arrays. If control line 18 is not energized and both stages of the configuration shift register are " one," both arrays of the pair are in operation, whereas if only one stage is " one" the respective array of the pair is operative alone and this leads to an error indication from the comparisons mentioned. The first array of every pair, or the second array of every pair, or both, can be rendered inoperative (isolated) by de-energizing a first or a second of two configure lines or both of them respectively, during a diagnostic mode initiated by the error indication. In the diagnostic mode, the control line 18 can be energized to connect the configuration registers and columns of selector triggers into a single shift register as shown, preventing any by-passing of the selector triggers. Binary control data can be entered into the configuration shift register 15 at 17. The arrays may be non-associative.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB5178669 | 1969-10-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1265014A true GB1265014A (en) | 1972-03-01 |
Family
ID=10461380
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1265014D Expired GB1265014A (en) | 1969-10-22 | 1969-10-22 |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS4827485B1 (en) |
CA (1) | CA922810A (en) |
DE (1) | DE2051348A1 (en) |
FR (1) | FR2065455B1 (en) |
GB (1) | GB1265014A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4717617B2 (en) * | 2005-12-08 | 2011-07-06 | 富士通株式会社 | Associative memory control device and method |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3290659A (en) * | 1963-12-30 | 1966-12-06 | Bunker Ramo | Content addressable memory apparatus |
-
1969
- 1969-10-22 GB GB1265014D patent/GB1265014A/en not_active Expired
-
1970
- 1970-08-24 FR FR7032154A patent/FR2065455B1/fr not_active Expired
- 1970-09-04 JP JP45077204A patent/JPS4827485B1/ja active Pending
- 1970-09-28 CA CA094172A patent/CA922810A/en not_active Expired
- 1970-10-20 DE DE19702051348 patent/DE2051348A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
CA922810A (en) | 1973-03-13 |
FR2065455B1 (en) | 1973-11-23 |
DE2051348A1 (en) | 1971-05-06 |
FR2065455A1 (en) | 1971-07-30 |
JPS4827485B1 (en) | 1973-08-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |