DE2051348A1 - Digital data storage system - Google Patents

Description

IBM Germany Internationale Büro-Matchinen Geielhdiaft mbH

Applicant:

Official file number: applicant's file number;

Boeblingen, October 16, 1970 jo-rz

International Business Machines Corporation, Armonk, NY 10504 New registration
Docket UK 969 012

Digital data storage system

The invention relates to a double memory arrangement existing digital data storage system.

Duplicate storage arrangements in a data storage system allow an effective error detection in a very simple way. For a system with associative memory that consists of there is duplicate associative memory arrangements, each of these arrangements receives the same input information. If both memory arrangements are working properly, the contents of the memory will be out at the end of the memory operation individual registers existing associative memory arrangements be identical. The states of the registers are continuously compared, if they are marked by setting the selector flip-flop during control. If a comparison shows a discrepancy, there is an error somewhere. After the identification of the properly working memory arrangement it is necessary to inaktivie the faulty memory array so that the faultless array is controlled independently while it transfers the data stored in it to at least one backup storage system.

The task is for such a storage system or a similar one of the invention is a simple and effective arrangement for determining the active or inactive levels the storage arrangements of a double storage

109819/1746

an existing storage system.

The invention consists in that a configuration register and several control devices are optionally arranged to to make one or both memory arrays active or inactive, depending on the contents of the configuration register.

Further features, advantageous configurations and developments the subject matter of the invention can be found in the subclaims.

The advantage that can be achieved with the invention becomes particularly clear when monolithic memories are used. In memory systems constructed in this way, a memory consists of a module with very small external dimensions. at In the development of these memory modules, there is a need to use as few external connections as possible to transfer data, To transmit control signals and electrical power to the module. By using the configuration register as a shift register is designed, only one connection is required to transmit data to a module, which is active or inactive Determine the states of the storage arrangements.

Another advantage is that the proposed technique is not only suitable for double use, but also for multiple storage arrangements can be used.

The invention is described in more detail below with reference to an exemplary embodiment illustrated by drawings. Show it:

1 shows a schematic representation of two storage systems according to the invention,

Fig. 2 is a block diagram of part of the logic circuit of the system according to the invention and

Fig. 3 is a block diagram of another part of the logi socket UK 969 O! 2 109819/1746

- 3 see circuitry of the system according to the invention.

Fig. 1 shows two associative memory systems 1 and 2. Die Storage systems 1 and 2 each consist of the duplicated associative storage arrangements IA, IB and 2A, 2B consisting of Word registers exist with the data collection lines 3 and 4 are connected via input / output registers. The memory arrangement IA is connected to the data bus lines 3 and 4 via the inputs / Output registers 5A and 6A connected, while the memory arrangement IB via the input / output registers 5B and 6B with the data bus lines 3 and 4 is connected. The registers 7A, 7B and 8A, 8B connect the memory arrays 2A and ^, respectively 2B with data bus lines 3 and 4.

It is necessary in the case of an associative memory, in which the data is not addressed by the storage location it occupies. Provide means for marking the word register or the word register of the memory to be addressed for successive read or write operations. For this purpose, each word register has a corresponding selector flip-flop which is set to a given stable state when the corresponding register has been selected for control. The state of the selector flip-flop is then used to switch read or write signals through to the word register. Fig. 1, the correspondent M schematically shows exploding word register 9A and 9B of the Speieheranordnungen IA and IB, along with their corresponding selector flip-flop circuits 1OA and 1Ob. The selector flip-flops of each memory arrangement are connected to one another in the manner of a shift register, so that the state of each selector flip-flop is shifted into the adjacent selector flip-flop by a memory operation with the designation "next (register)". At the head of the shift register chain, formed from the selector flip-flops, there is a line labeled "next (information) in", which represents an input line for the last flip-flop. The last selector flip-flop in the chain

Docket UK 969 012 10 9 819/1746

provides an output signal to a line labeled "next (information) out" which is connected to the "next in" line of another storage system. This arrangement is shown in FIG. 1 _r in which the “next, in” line into the memory system 1 is designated by 11. Since the system consists of duplicated storage arrangements, the line 11 is also split in order to form corresponding inputs for the selector toggle circuits of each arrangement. The respective outputs of the last flip-flop are combined to form the “next out” line 12, which is connected to the “next in” line 13 of the memory system 2. The “next out” line of the storage system 2 is denoted by 14.

According to the invention, each memory system has a configuration shift register. The memory system 1 has the configuration register 15 and the memory system 2 has the configuration register 16. Each register is a two-digit binary Shift register and connects the "next out" line of one memory system to the "next in" line of another Storage system. So is the input to the configuration register 15 is the "next out" line 17 from a storage system (not shown) and the output is the "next in" line 11 of the memory system 1. The input to the configuration register 16 is the "next out" line 12 of the memory system 1 and the output of register 16 is the "next in" line 13 of memory system 2. Furthermore, each is configuration register connected to the configuration control line 18.

Flg. 2 shows, with reference to the configuration register in FIG. 1, details of how control signals are sent from it Register are generated. As already mentioned, the configuration register is a two-digit binary register. In the In the present description, these locations are designated by P and Q, respectively. Lines 19 and 20 are each energized, when the digits P and Q each store a binary one.

Docket UK 969 012 109819/1746

Zm further 1st vorcreaehen a logic network that consists ans the UKD circuits 21 to 23, the OR circuit 24 and the inverter "25 and 26th The set is arranged in such a way that an output signal is present on the line 27 of the OR circuit 24 if (nods Ψ and O) or (P and not Q) contain a binary in. The logic network also supplies an output signal on the output line 28 of the AND circuit 23 if P and Q of the configuration register 15 do not contain a binary one.

The line 19 also represents an input line for the AND circuit 29, the other input of which is formed by a “configure A” line 30. Similarly to Gani, line 20 also represents an input of AND circuit 31, the other input of which is formed by a “configure B” line 32. The configuration lines IB, 30 and 32 are used in connection with a finest diagnostic method that follows the discovery of an error. The configuration of the storage system takes place in two stages. Xn the first stage it is determined whether the storage system is to be used as a Gansee. If the configuration control line IQ is not energized and if the content of the configuration control register is as follows: PQ- binary one, then the storage system is normally used. As shown in FIG. 2, in this case both lines 19 and 20 carry the output signal of the "control" P and Q clff registers 15. Nominal configuration line 18 carries a signal and if the content of the configuration is expensive register β follows is "f - Q" binary MuH, then the ipeichersyste "is not used In this' case, · the line leads 28 fin signal and causes the ^M nlchste inside" - and ". next addition" -Leitungeη be bypassed . It also blocks the drivers and latching circuits that connect the "pelohersyste *" to the data base lines. The apeichersYSt ·· wir4 βμί dieae Heise isolated and it is out of order. Am 8p * 4.chfrsy§te »can either fit for use Krsaneystf · ο4 · Γ after finding a non-healing

Docicet UK H9 OU 1 Q 9 8 1 9/1 7 4 6 BATH ORIGINAL

isolated error in the system. The above description clearly shows that the state of a storage system? - in operation or isolated - when the configuration control line 18 carries no signal, only from the contents of the configuration register depends. The last case to be considered in this context, in which the! Configurations Control line 18 carries no signal is when either the Place P or Q, but not both, contain a binary one. In this case the line 27 carries a signal which, w ^ e will be explained below, leads to an error condition.

The second level of the configuration control concerns Duplex storage arrangements in the storage system, for example storage arrangements IA and IB of storage system X.

The "configure A" line 30 and the "configure s" line 32 is compatible with all storage systems, for example with the storage systems 1 and 2 in Fig. 1 connected in parallel. The output line 33 of the AND circuit 29 controls the active one or inactive state of the memory arrangement IA of the memory system 1, while the output line 34 of the AND circuit 31 the active or inactive state of the memory arrangement IB des Speiehersystems 1 controls. When the output line 33 or 34 carries a signal, then the device that controls it is im active state. If an output line 33 or 34 is no If the output signal leads, then the drivers are ujad receiving circuits in the connection of the controlled arrangement with the data exchange lines locked and the arrangement is effectively isolated.

The output line 33 then carries no signal when the "configure A "-t # itation 30 k * in signal leads P4 to the bit position P of the configuration register 15 contains fine binary zero. Similarly, u »fin signal ajif djir 34 §wfr * ch ^? Ueri! #It «WI * 4 ^ f" ko ^ figuritrf B "-I # i41; u $ g

pi sin Q ^ i 1 qpti / u4§

Lead signal and the bit position Q of the configuration register contain a binary one. In normal operation, lines 30 and 32 carry signals, and thus when the content of the configuration register is different than P = Q, the register control of one and only one of the storage arrangements of the System isolated. This leads to an immediate error signal which is generated because the contents of the input / output register or the states of the selector flip-flops of two storage arrangements will not be the same with the memory arrays after the following operation.

Once an error signal has been detected, all storage systems are switched to the "diagnosis" mode. The diagnostic method involves independent operations on each memory array such as the "configure A" line 30 and the "configure B" line 32 independent signals lead or not, depending on the requirements of the diagnostic method, to one or the other of the memory arrangements of the isolate the diagnosed storage system. Because the lines 30 and 32 are connected in parallel to all storage systems, the storage arrangements in all systems are simultaneously isolated. This has no effect on data that are stored in other arrangements than the diagnosed ones, since themselves the operations do not extend to these other arrangements.

The configuration control line is in the "Diagnosis" operating mode 18 the required signal. This turns the configuration registers of all storage systems into a chain of shift registers connected from the registers, the selector flip-flops of all storage systems and the lines "next in" and "next out" consists. In particular, the signal on the configuration control line blocks the bypass route of the lines "next in" and "next out", which is present when the configuration register has the following content: P = Q = binary zero. Binary data can be stored along the chain in the configuration register of the faulty system and the replacement system

Docket UK 969 O ₁₂ 109819/1746

be pushed, which latter is put into operation in this way.

Fig. 3 shows the logic circuit "by which the" next in "and" next out "lines are selectively bypassed. The "next out" line 17 in Figure 1 is across the AND circuit 35 with the configuration register 15 and via the AND circuit 36 with the "next addition" line 12 of the Storage system 1 connected, which is effectively the "next in" line of storage system 2 is. The only other input of the AND circuits 35 are those combined via an OR gate O Lines 19 and 20, which then carry a signal when the positions P or Q of the register 15 are a binary one contain. The other inputs to the AND circuit 36 are each connected to an inverter 37, which in turn connects to the configuration control line 18 is connected and connected to an AND circuit 33, which is also shown in Fig. 2 and a Signal leads if and only if both positions P and Q carry a binary zero. The arrangement of this circuit is then further constructed so that line 17 is connected to line 12, i.e. the "next in" and "next." addition "lines of the storage system I are bypassed if and only if the configuration control line has no signal and all positions in the configuration register contain a binary zero.

The foregoing describes a duplicated memory system that includes a configuration shift register, whereby the active or inactive state of the entire storage system or a selected half of the system can be controlled.

Docket UK 969 O ₁₂ 1098 19/1746

Claims (9)

PATENT CLAIMS E. More arrangements consisting of duplicated storage Digital data storage system, characterized in that a configuration register (e.g. 15; Fig. 1) and control means (Fig. 2, Fig. 3) are optionally arranged to accommodate one or both of the memory arrays (e.g. IA, IB; Fig. 1) active or inactive, depending on the content of the configuration register, close. 2. Storage system according to claim 1, characterized in that the configuration register (eg 15; Fig. 1) from a d two-digit binary shift register, with each digit assigned to a different memory arrangement (e.g. IA, IB) is. 3. Storage system according to claim 1 or 2, characterized in that the active or inactive state of a memory arrangement by combining the contents of the configuration register and the status, signal-carrying or not, one configuration control line (e.g. 18) associated with a particular memory array. 4. Storage system according to one or more of claims 1 to 3, characterized in that the memory arrangements I (e.g. IA, IB; Fig. 1) designed as an associative memory are. 5. Storage system according to claim 4, characterized in that each storage arrangement (e.g. IA; Fig. 1) is a group of selector flip-flops (1OA), each having a selector flip-flop circuit of a row of the memory arrangement is assigned and wherein the selector flip-flops are connected in the manner of a shift register. Docket UK 969 012 109819/1746 6. Storage system according to claim 5, characterized in that the shift registers formed from the selector flip-flops (e.g. 1OA, 1OB; Fig. 1) in parallel between an input and Output line are switched on and that the serial Output of the configuration shift register 15 is connected to said input line. 7. Storage system according to claim 1, characterized in that several duplicated storage arrangements (e.g. IA, IB, 2A, 2 B; Fig. 1), each pair of memory arrays (e.g. 2A, 2B) having its own configuration register (e.g. 16) and own control arrangements (Fig. 2, Fig. 3) according to claims 1 to 6 has. 8. The memory system of claim 7 having pairs of memory arrays according to claim 3, characterized in that two configuration control lines are provided, one of which one the active or inactive state of a memory array of the pair and the other line the active or inactive Controls the state of the other memory array of the pair. 9. Storage system according to claim 7 or 8, with a pair of arrangements according to claim 6, characterized in that the output line with the serial input of the configuration shift register of the other duplicated pair of storage arrays. Docket UK 969 O ₁₂ 1098 19/1746 Blank page