GB1264181A - - Google Patents

Info

Publication number
GB1264181A
GB1264181A GB1264181DA GB1264181A GB 1264181 A GB1264181 A GB 1264181A GB 1264181D A GB1264181D A GB 1264181DA GB 1264181 A GB1264181 A GB 1264181A
Authority
GB
United Kingdom
Prior art keywords
shift
counting
gates
flip
marked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1264181A publication Critical patent/GB1264181A/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/54—Ring counters, i.e. feedback shift register counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers

Abstract

1,264,181. Counters; shift registers. STARK. STROM - ANLAGENBAU KARL - MARXSTADT VEB. 20 Aug., 1969, No. 41560/69. Headings G4A and G4C. A gated circuit, according to which of its terminals are marked, can operate as a reversible binary counter or as a shift register. A reset pulse on 0 sets all flip-flops to zero. For forward counting LV is primed, while RL is marked for reverse counting. Counting requires a mark on lead LZ, shift a mark on SL. Potential on E together with a clock pulse CP reverses FF1. For forward counting gate I1 becomes 0 and II1 changes to 1, so priming both inputs of FF2. The second clock pulse restores FF1 and sets FF2 to 1, and so on. For reverse counting the gates I1-I3 always have an output 1 but the gates III1 &c. have output 0 whenever the related flip-flop is false, so priming the succeeding flip-flop. The modified circuit of Fig. 3 is arranged for binary-coded decimal operation with carry from NAND gate II/III4 accompanied by forward or reverse marking of the higher denomination from gate NV or NR, as the case may be. Shift.-The several count control leads except CP and E are disabled and shift prime lead SL marked. The required input is applied at SW and the gates IV, V for each flip-flop control gates I-III to shift the pattern along at each clock pulse.
GB1264181D 1969-08-20 1969-08-20 Expired GB1264181A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB4156069 1969-08-20

Publications (1)

Publication Number Publication Date
GB1264181A true GB1264181A (en) 1972-02-16

Family

ID=10420261

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1264181D Expired GB1264181A (en) 1969-08-20 1969-08-20

Country Status (1)

Country Link
GB (1) GB1264181A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2154771A (en) * 1984-02-21 1985-09-11 Mirowski Mieczyslaw Digital rate averaging circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2154771A (en) * 1984-02-21 1985-09-11 Mirowski Mieczyslaw Digital rate averaging circuit

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees