GB1256068A - Improvements in or relating to logic circuit arrangements - Google Patents

Improvements in or relating to logic circuit arrangements

Info

Publication number
GB1256068A
GB1256068A GB5579867A GB5579867A GB1256068A GB 1256068 A GB1256068 A GB 1256068A GB 5579867 A GB5579867 A GB 5579867A GB 5579867 A GB5579867 A GB 5579867A GB 1256068 A GB1256068 A GB 1256068A
Authority
GB
United Kingdom
Prior art keywords
pulse
input
gate
clock
negative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5579867A
Inventor
Peter Eric Krebs
Alan Ryder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB5579867A priority Critical patent/GB1256068A/en
Publication of GB1256068A publication Critical patent/GB1256068A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/002—Pulse counters comprising counting chains; Frequency dividers comprising counting chains using semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
    • H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H03K5/15093—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using devices arranged in a shift register

Abstract

1,256,068. Transistor pulse circuits. PLESSEY CO. Ltd. 24 Jan., 1969 [7 Dec., 1967], No. 55798/67. Heading H3T. [Also in Divisions G1 and H1] In a logic circuit, a capacitance C O , Fig. 3, which is inherent in a device such as a MOST M1 receiving an information input V I , accepts and stores the information under the control of a clock pulse #, applied through a capacitor C and supplying the power for the logic circuit. The circuit acts as an inverter; a negative input ("1") turns on the MOST M1, and the capacitor C O maintains O V output; a zero voltage input ("0") turns M1 off and the output V O is a negative pulse derived from the negative clock pulse by the potential divider C, Co. A delay element (Fig. 4, not shown) uses two of the Fig. 3 inverters in cascade, and controlled from separate clock pulse sources # 1 and # 2 . Two (or more) of these elements form a delay line (Fig. 6, not shown), in which the clock pulses must overlap if a two phase source is used, but not if three or more phases are used. "Write-in" to an intermediate stage of such a two-phase delay line is effected (Fig. 9, not shown) by a series pair of MOST's (M16, M17) receiving respectively a negative control pulse and the information input, so that when both are negative, the next MOST stage (M13) is turned on; at the same time the control pulse turns on a MOST (M15) in parallel with a preceding stage MOST (M11) to inhibit same. In an alternative "write-in" arrangement, the pair (M16, M17) is replaced by a gating MOST (M19) with its source-drain path in the input line to the gate of one stage (M14) of the delay line, the gating MOST (19) having the control input at its gate. Shift/storage circuits use bi-stable pairs of the Fig. 3 inverters (Figs. 11, 12, 13, not shown). A plurality of cascaded inverters (Fig. 15, not shown) operates from a single phase clock pulse source, but the number of stages is limited due to the progressive reduction of pulse amplitude and steepness of pulse edges through the stages. A counter/register (Fig. 18, not shown), said to be known, is constructed with the Fig. 3 inverters and consists of: three MOST's (M33, M34, M35, Fig. 19, not shown) with a common drain capacitor (C19) receiving # 1 clock pulese, forming a NOR gate; an AND gate having MOST's (M37, M38) fed from the NOR gate and from an input Do and controlled over capacitors (C20, C21) from the two phases of the clock source; and a bi-stable delay stage (as in Fig. 13, not shown) comprising three MOST's (M39, M40, M42) and an inhibit MOST (41). An integrated circuit construction is disclosed. Bipolar transistors may be used. Instead of a MOST, an opto-electronic diode (Do, Fig. 24, not shown) may be used as the device whose inherent capacitance stores the information. Here, the clock pulse, or "address", is applied through a capacitor (C26) as before to charge the diode Do capacitance. If the information input, in the form of light falling on the diode, causes the capacitance to discharge, then a predetermined voltage signal applied subsequently to C26 fails to turn on a MOST (M52); but if the diode (Do) has held its charge, the predetermined voltage will be sufficient to turn on the MOST (M52).
GB5579867A 1967-12-07 1967-12-07 Improvements in or relating to logic circuit arrangements Expired GB1256068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB5579867A GB1256068A (en) 1967-12-07 1967-12-07 Improvements in or relating to logic circuit arrangements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB5579867A GB1256068A (en) 1967-12-07 1967-12-07 Improvements in or relating to logic circuit arrangements

Publications (1)

Publication Number Publication Date
GB1256068A true GB1256068A (en) 1971-12-08

Family

ID=10474916

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5579867A Expired GB1256068A (en) 1967-12-07 1967-12-07 Improvements in or relating to logic circuit arrangements

Country Status (1)

Country Link
GB (1) GB1256068A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2156564A1 (en) * 1971-10-04 1973-06-01 North American Rockwell
FR2235456A1 (en) * 1973-06-30 1975-01-24 Sony Corp
FR2336004A1 (en) * 1975-12-17 1977-07-15 Itt MOS POWER STAGE FOR CLOCK SIGNAL GENERATOR
FR2339996A1 (en) * 1976-01-31 1977-08-26 Itt INTEGRATED CLOCK PULSE CONFORMING CIRCUIT

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2156564A1 (en) * 1971-10-04 1973-06-01 North American Rockwell
FR2235456A1 (en) * 1973-06-30 1975-01-24 Sony Corp
FR2336004A1 (en) * 1975-12-17 1977-07-15 Itt MOS POWER STAGE FOR CLOCK SIGNAL GENERATOR
FR2339996A1 (en) * 1976-01-31 1977-08-26 Itt INTEGRATED CLOCK PULSE CONFORMING CIRCUIT

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