GB1244239A - High speed reciprocal and quotient computing apparatus - Google Patents

Abstract

1,244,239. Divider. TIME SYSTEMS CORP. 28 Nov., 1969 [29 Nov., 1968], No. 58389/69. Heading G4A. The invention relates to dividers particularly to dividers for obtaining a digital frequency value from a period. A period register 20 having a plurality of Decade Counter Units DCU contains a number representing a period. A transfer unit 30 enabled by pulses from a control Decade Unit passes the contents of the register 20 to a transfer unit 60 containing two sets of gates 1 S -8 S , 4 R -11 R . Each element of the transfer unit is coupled to a gate in each set and the gates are coupled to an accumulator 40 with gates 1 S -8 S coupled to stages A 1 -A 8 respectively and gates 4 R -11 R coupled to stages A 4 -A 11 respectively. The gates 1 S -8 S are enabled by the set output of a flip-flop 80 and the gates 4 R -11 R are enabled by the reset output. Initially flip-flop 80 is reset so that the contents of register 20 are transferred to the accumulator effectively multiplied by 1000. Nines detectors coupled to stages A 12 -A 14 of the accumulator feed an AND gate arranged to set flip-flop 8 when the most significant three digits of the accumulator are each nine. The set flip-flop causes the contents of register 20 to be transferred normally. The flip-flop also controls AND gates 90 R , 90 s causing a pulse indicating that the contents of the register 20 have been transferred to enter either stages F 1 or F 4 of the frequency register counter so that the counter is incremented by 1 or 1000. When the accumulator is full and overflows the Control Decade Unit is stopped, and the counter contains the required quotient. The apparatus may also be used to divide by presetting the accumulator to a number such that the accumulator would overflow if the dividend was added to it, entering the divisor in the period register 20 and performing the division operation as described above.