GB1225801A - - Google Patents

Abstract

1,225,801. Transistor switching circuits. AUTOMATIC TELEPHONE & ELECTRIC CO. Ltd. 6 May, 1969 [15 May, 1968], No. 23154/68. Heading H3T. [Also in Division G4] A switching circuit Fig. 1 (providing, for example a write current for a magnetic recording medium) has three similar conductivity type transistors TX, TY, TZ connected as shown to an inductive load, such as the primary of a transformer T, whose centre tap is connected to the supply - V through an inductance L the constant current in which is alternately switched through TX, TY; and a drive circuit (Fig. 3, not shown) is arranged to turn on all three transistors to build up the current in L to the required value, before push-pull operation starts. TX conducts before TY in each bit period to write a " 1 " and TY before TX to write a "0". The driver circuit (Fig. 3, not shown) includes NAND gates (G1-G9) and two bi-stable circuits (A, B) each of which also consists of NAND gates (E1-E6, Fig. 2, not shown) arranged in three pairs. One output (Q) of the bi-stable outputs (Q, #Q) adopts the state of the input (D) when a clock pulse (CP) occurs; and asynchronous setting (Q = 1) and resetting (Q = 0) is effected by a O input to, respectively, the preset input (P) and the clear input (C) which are normally held at 1. In the drive circuit (Fig. 3, not shown) the write signal WS (waveforms, Fig. 4, not shown) is inverted (G5) to turn on TZ, Fig. 1. The Q output of the first bi-stable (A) drives the transistors TX, TY via respective gates (G1, G4) one of these gates (G4) being supplied through another gate (G3) to provide the inversion necessary for push pull operation. This inversion (by G3) is effectively cancelled, however, during the initial build-up of current in L, to allow TX and TY to both conduct, by means of a further gate (G2) controlled by the second bi-stable (B) which maintains its reset state for one complete clock pulse cycle after the signal (WS) starts. On the next clock pulse after the start of the write signal, the second bi-stable (B) is set, to supply: a 1 to gates (G6, G8) receiving the data signal (LI) thereby enabling the first bi-stable (A) to be controlled by the data (LI); and a 0 to the gate (G2) allowing the X and Y gates (G1, G4) to supply antiphase signals. The first bi-stable (A) then controls the gates (G1, G4) to drive the write circuit of Fig. 1. The 1 and 0 edges of the write signals are defined by the negative going edges of the clock pulses (CP).