US2747110A - Binary magnetic element coupling circuits - Google Patents

Description

May 22, 1956 J. P. JONES 2,747,110

BINARY MAGNETIC ELEMENT COUPLING CIRCUITS Filed Feb. 14, 1955 L L AovAucms PULSES ADVANCING do PULSES 4e i I 44 "P .I I l i I 1 SWITCHING TIME OF 1 I TRANSFEREE CORE I l I J F|G.2

SWITCHING TIME OF UNLOADEDI TRANSFEROR com: I k J Y SWITCHING TIME OF LOADED TRANSFEROR CORE Bmux 5' PARTIAL 6Q READOUT +Br -81 54 PARTIAL READOUT 2 Bmin- INVENTOR.

JOHN PAUL JONES BY ATTORN EY BHNARY MAGNETIC ELEMENT CUUPLING cmcrnrs John Paul .i'ones, Pottstown, Pa, assignor to Burroughs Corporation, Detroit, Mich, a corporation of Mirth:- gain Application February 14, 1955, Serial No. 487,857

9 Claims. (Cl. 307-88) This invention relates to transfer circuits between binary magnetic storage elements in general, and more particularly to transfer circuits which may be used in a two core per bit type of magnetic shift register.

A two core per bit shift register is so-called because it requires two biary magnetic cores to complete the transfer of information from one core to the next core in an array of cores in a computer or logic solving circuit. At a given time period T1, a pulse is sent to one core to store information in it. At the same time that this core is actuated so that it is switched to store a l, the core in the array adjacent to said switched core is cleared or switched to a so that it is free to receive information. At a time period T2 after T1, the core in the -1 state is cleared of its 1 and the cleared l is transferred .to the adjacent core that is in a 0 state. Thus two separate cores are needed to store a single binary bit 1 and cause transfer of the 1 from one core to another core. Thus, the shift register needs two cores to store and transfer this single bit of information, and is called a two core per hit shift register.

in shifting a core from one state to another, one relies on a transfer circuit to read a 1 out of a core and transfer said 1 into a core that is generally previously cleared to a 0" state. Transfer circuits may require that information travel along the array of cores in a given direction. it is desirable to provide circuits such that there will be no transfer of spurious signals anywhere along the array of magnetic cores when transferring 0 signals. An example of circuits designed in this manner is found in United States Patent No. 2,683,819 to Rey.

However, transfer circuits for a two core per bit shift register of the prior art type, while they may avoid the transfer of spurious pulses, entail a number of concomitant defects. One requirement of such transfer circuits is that the switching core (also called the driving or transferor core) must continue switching until the driven or transferee core completes its switching. The switching time of the transferor core must be longer than the switching time of the transferee core to assure that the latter will complete its switching prior to the removal of energy to the transferee core through the transfer circuit. Since it is the switching of the transferor core that supplies the energy through the transfer circuit to the transferee core, the transferor core must continue its switching at least until the transferee core has switched. in a computer device employing such a transfer circuit, the switching time must take into account the worst pos sible conditions and thus computations are generally slowed down.

Moreover, transfer circuits of the type employed in the prior art require diodes in the transfer circuits to assure transfer of energy in a single direction around the transfer circuit. Diodes are power dissipative elements and their presence in the transfer circuits of a two core per hit shift register imposes upon the designer of the shift register the need to supply additional energy to the advancing pulses that switch the transferor cores to allow for RQQ said dissipative losses through the diodes. Also these transfer circuits depend upon a large current flow in the trans-fer loop thus increasing transient problems and producing low transfer efliciency.

In order to overcome the time losses involved in the limitation that the switching time of the transferor core be longer than the switching time of the transferee core, a regenerative transistor circuit is coupled to the transferee core and is utilized in the transfer loop to form the means for receiving information stored in the transferor core. The regenerative transistor circuit requires only that it be triggered to initiate its operation, and once the triggering has begun, there is no need to prolong the switching time of the transferor core. The regenerative cycle of the transistor, once it is triggered, continues until the transferee core has completely switched. Thus, by this invention, the switching time of the transferor core need not be more than the switching time of the transferee core since the transferor core need only supply energy long enough to trigger the regenerative circuit. Once triggering has begun, the transistor provides amplified selfsustaining current to the transferee core independently of the transferor core, and until the transferee core has completed its switching.

Thus, the employment of the transistor circuit in a transfer circuit of a shift register in the manner set out hereinafter avoids the need for diodes and high current in the transfer circuit.

Therefore it is an object of the present invention to provide a high speed shift register.

A further object of the invention is to cut down on energy losses in the transfer circuit of two binary magnetic cores.

A still further object is to employ a regenerative transistor circuit to receive input signals for a binary core so as to reduce the critical operating requirements formerly imposed upon transferor cores and coupling circuits.

Further objects and features of the invention will be found throughout the following specification which describes the invention in greater detail. For a more complete understanding of the invention the specification may be considered in connection with the accompanying drawings, in which:

Fig. l is a circuit diagram of an embodiment of the instant invention;

Fig. 2 is a waveform chart illustrating switching time criteria of a transferor core and a transferee core which are considered in design of transfer circuits of a shift register; and

*Fig. 3 is a hysteresis loop of the binary magnetic cores used as a storage medium in the invention.

In consideration of Fig. 1, there are shown three binary magnetic cores 2, 4, and 6 that compose three of the many cores that may be employed in alternation to store and release information to adjacent cores. Advancing current from sources 8 and 10 traverses conductors 12 and 14 along the direction of arrows l6 and respectively flows through windings 17, and windings if; and 20. The advancing pulses from source 8 are timed pulses that, during a first designated time period T1, periodically enter the dotted terminal of a winding such as winding 17 to link core 4- with the flux created by said advancing pulses through said winding. It is understood that alternate cores will receive pulses at a similar winding at the same time as core 4 by advancing pulses along conductor 12.

By convention, when current enters a dotted terminal of a winding associated with a core, the flux produced by said current will tend to switch such core to a 0 state. In a similar manner, advancing pulses from source 10 appear at a time period T2 after core 4 and its associated cores have been switched or cleared to a 0 state.

These pulses serve to switch cores 2, 6, and their associated cores to a state by causing current to enter through the dotted terminals of windings 18, Ztl and similar alternate windings not shown.

It will be seen that first one .pair of cores 2 and 6 are cleared of their information. The information is passed through transfer loops 22 and 24 respectively from cores 2 and 4 to adjacent cores 4 and 6. Transfer loop 22 comprises an output winding 26 and trigger winding 28 joined by conductor 3i). Winding 28 terminates at the base of 32 of a transistor whose emitter electrode 3% is grounded and collector electrode 36 is in series connection with switching winding 38.

Assuming that core 2 is in a 1 state and core 4 in a 0 state when an advancing pulse from source arrives at winding to shift core 2 to a 0. Emitter electrode 34 is biased by a suitable low power D. C. source not shown with the potential at winding 26 so that said emitter electrode is negative with respect to base 32. to base 32 through winding 23, conductor 36 and winding 26 until a threshold above noise level is reached. When core 2 is switched from a l to a 0 the threshold level is overcome and current enters winding 26 in such a manner as to oppose this switch to a O.

Such entry would be through the undotted terminal of winding 26, causing current to flow through transfer loop 22 from ground, through emitter electrode 34-, base 32, winding 23, then through the undotted terminal of winding 26 to the terminal of a source of potential. As soon as current is initiated through trigger winding 23 so as to overcome the back bias and pass through base 32 and emitter electrode 34, amplified collector current will flow in the direction of arrow 35 into the undotted terminal of winding 38, through ground, emitter electrode 34, base 32, collector 36 and back to the undotted terminal of winding 38. The core 4 will begin switching as soon as the collector current begins to follow the emitter current of the transistor. The core 4, once the trigger winding initiates the flow of current through the emitter electrode 34, will continue to be switched by the regenerative cycle of the transistor even if core 2 has completed its switching cycle. Such regeneration takes place because the switching of core 4 to its 1 state due to current flowing into the undotted terminal of winding 38 will induce a voltage in winding 28, said induced voltage opposing such switching to the 1 state. Such induced voltage will cause current to flow into the dotted terminal of winding 28, such current being in the same direction as that which triggered current to flow through the undotted terminal of winding 38. Regenerative switching continues until core d has completely switched to its 1 state. No transfer is effected through transfer circuit 22, however, upon switching of core 4.

The advantage of the transistor circuit of this in vention can be better seen by comparing the switching times of cores in a conventional shift register with the switching times of the cores in the instant invention. In prior art transfer loops, when a l is read out from a core and read into an adjacent core, it was necessary to continue the switching of the transferor core until the transferee core was completely switched. Curve 40 whose continuation 42 reaches the base of the time scale of the diagram, represents the time it takes for an unloaded, or switching transferor core, to complete its switching. Since low current flow occurs in the transfer loop coupling the transferor core with the transferee core while the transferor core is switching, it is seen that this current flow level continues for the period 34 until the transferee core is completely switched. inherently it is a requirement of conventional transfer loops that the switching time 4.2 of the transferor core be longer than that of the transferee core to assure that switching energy applied to the transferee core until it is switched.

Moreover, when the transferee core has completed its The resulting bias prevents current flow i switching, the core presents a low impedance thus passing much higher current and becoming a load to the transferor core which causes the switching rate of the transferor core to slow down. Extension 46 of curve 49 represents the time necessary for the transferor core to complete switch ing after point P which represents the time when the transferee core has completed its switching. The switching time of the transferor core tails out and subtracts from the overall speed otherwise available with the shift register. The instant invention, by employing a regeneratively coupled transistor in the transfer loop, not only avoids this inherent delay in prior art transfer loops, but allows for the switching time of the transferor core to be less than that of the transferee core. Thus the transferor winding is never loaded down by a low impedance circuit of a switched core since the transistor input circuit impedance always remains high, thereby eliminating any tail out effect. In addition, the self-switching regenerative circuit requires switching of the transferor core only long enough to trigger the regeneration, and itself switches the transferee core as quickly as possible. By such means a high speed shift register circuit is attainable, and furthermore, circuit design is not restricted to formerly critical values.

In Fig. 3 there is seen a hysteresis loop of a binary magnetic core where point +Br represents the storage of a l in a binary core and represents the positive remanent storage state of a core, and Br represents the negative remanent storage state of a core or the storage of a 0 in the core. Point 131 represents the maximum flux obtainable in shifting a core to a 1. When the magnetizing field is removed from the core after the saturation point B1 has been reached, the core will fall back to its remanent state +Br. The closer the hysteresis loop is to a square configuration, the closer will point +Br be to the point Bmax. Similarly, point Br is the negative remanence state and Bmln is the maximum saturation of the binary core in the negative direction of magnetic induction.

To the extent that cores are not square, it can be seen that when a core is in a 1 state, as represented by the point +Br, and an attempt is made to drive said core to a 1 state, the magnetic induction of said core will increase to point B1 and continue along saturation curve 48 and then drop back to point +Br along line 59. The flux change between +Br and Bma}; during such attempted switching of a core from a l to a 1 is termed a partial readout and represents noise in the transfer circuit. Similarly, the flux change between points -Br and Bruin is a partial readout representing noise obtained when a core in the 0 state has a magnetizing field applied to the winding associated with said core that tends to drive said core to a 0 but merely drives the core along saturation curve 52 back to point -Br along line 54 when the magnetizing field is removed.

The instant invention not only provides for speeding up of the transfer of information but also prevents the transfer of noise in the circuit. Thus reconsider Fig. l, and assume that core 4 through its associated winding 17 is actuated by a pulse from source 8 at time period T1 to tend to switch said core to a 0 while it is already in a 0 state. Core 4 will not switch but it will be driven, due to the lack of squareness of the core along lines 54, 52, through a partial readout, resulting in noise. In order to prevent this partial readout from being transferred as noise, or as a partial I through the transfer loop 24, a suitable back bias is placed on the base electrode of the transistor 62, said bias being sufiicient to overcome the anticipated maximum negative output voltage resulting from the noise signal. The driving of an unsquare core 4 already in the 0" state toward the 0 state will produce a slight negative potential at the undotted terminal of winding 56 which nega tive potential appears on the base of transistor 62. Such negative potential might trigger transistor 62 into conductivity. Such undesired triggering is avoided by employing sufficient positive bias on the base electrode of transistor 62 so that the latter bias is sufiicient to overcome the anticipated maximum negative voltage appearing at the base of a transistor, such as transistor 62 in transfer loop 24 due to the presence of a noise signal. Consequently there is no forward transfer of noise from a transferor core to a transferee core. It is also noted that when core 4 is switched from its 1 state to its 0 state, a positive potential is created at the dotted terminal of winding 28, which positive potential appears at transistor base 32, such positive potential being additive to the cut-off bias already being applied to the transistor, preventing any backward fiow of information through transfer loop 22. Thus there is no transfer to the left of core 4 of information during readout and the transfer of noise in a forward direction is nullified.

Transfer loop 24 is similar to transfer loop 22 wherein output winding 56, conductor 58, trigger winding 60 and transistor 62 and read-in winding 64 play substantially the same role as their counterparts 26, 30, 28, 32, 34, 36 and 38 in transfer loop 22.

Thus one avoids, by using the transistor circuit of this invention in a novel transfer loop, the need for a diode in a transfer loop and its attendant energy losses. One also attains the elimination of noise simultaneous with the speeding up of the transfer of information through the array of cores in the shift register by allowing for the switching time of the transferor core to be less than the switching time of the transferee core. Finally, the regenerative cycle of the transistor circuit during readin of information assumes dependability of core switching because even if the amplification of the transistor should drop, the core being switched by the regeneratively coupled switching winding will only take longer to switch, but the regeneration always will continue until switching is completed. Thus relatively poor quality cores (cores of low squareness ratio), can be employed without affecting adversely the operation of the shift register. During read-in of a 1 into core 4 from core 2, the signal developed across the trigger winding 28 is a voltage drop, not a current flow, and the voltage induced in switching winding 38 produces sustaining signal voltage. This regenerative voltage may be greater than the output voltage of output winding 26 of core 2 as seen at trigger winding 28. Thus the energy at core 2 from source needed to switch core 4 is very little more than that needed to switch core 2 as contrasted to the usual requirement that enough energy be supplied for switching both cores. Thus, the transfer loop employing the regenerative transistor circuit permits use of a low power advancing pulse source because of energy saving in the transfer circuit.

From the foregoing description of the invention, it is clear that the present technique of employing transistors in transfer loops of a two core per bit shift register results in a high speed, accurate, noise-free transfer of information through the array of cores in said shift register. Accordingly, those novel features believed descriptive of the invention are defined with particularly in the appended claims.

What is claimed is:

1. In combination, a transferor core and a transferee core, a transfer loop coupling said cores comprising a series circuit including an output winding about the transferor core, an amplifier device, a trigger winding about the transferee core, a switching winding about said transferee core, and a regeneratively coupled circuit including the amplifier device connected to said trigger and switching windings.

2. A combination as defined in claim 1 wherein fixed bias means is coupled with the amplifier device in the transfer loop to prevent current fiow through the loop from induced potentials falling below a threshold level.

3. A combination as defined in claim 1 wherein the amplifier device is a transistor, and two leads of the transfer loop are coupled to the transistor between the base and emitter electrodes.

4. A combination as defined in claim 3 wherein the switching winding is coupled to the transistor collector electrode, and the switching winding and trigger winding terminals are coupled to the transistor electrodes in opposite sense.

5. In combination, a transferor binary core and a transferee binary core, a transfer loop coupling said cores comprising an inductive output winding associated with said transferor core, a trigger winding connected to said output winding, a regeneratively coupled transistor circuit connected to said trigger winding and supplying, when conducting current, switching energy to said transferee core, the transistor circuit being connected to present relatively constant input impedance to said output winding so as to avoid high current in the transfer loop upon the switching of said transferee core.

6. In combination, a transferor binary core and a transferee binary core, means for switching the transferee core in response to the switching of the transferor core comprising an output winding associated with said transferor core, a trigger winding associated with the transferee core connected in series with said output winding, a transistor, an input electrode of said transistor coupled to said trigger winding, and a regenerative winding coupled to a further electrode of said transistor and associated with said transferee core so as to create a sustaining flux linkage between said regenerative winding and said trigger winding during switching of the transferee core.

7. A two core per bit shift register comprising in combination, alternate transferee binary cores and transferor binary cores coupled in a cascade circuit, means for directly reading into the transferee cores the information read out of the transferor cores comprising an output winding associated with said transferor cores, a trigger winding associated with the transferee cores connected in series with said output winding, a transistor, a transistor input circuit connected to said trigger winding, a regenerative transistor output circuit including a regenerative feed back winding forming the input winding for said transferee cores, and means for alternately interrogating the cores in said cascade circuit to produce a readout signal in said output winding and to reset the cores in a condition to receive input information.

8. In a two core per bit shift register, a transferor binary core and a transferee binary core, a transfer loop coupling said cores comprising an output winding associated with said transferor core, a triggering winding connected to said output winding, a regeneratively coupled transistor connected to said triggering winding, and means for supplying cut-off bias to said transistor, said bias tending to be overcome upon the switching of the transferor core and attendant passage of current through the output winding and triggering winding of said transfer loop.

9. In combination, input and output binary magnetic cores, a. transfer loop conductively coupling said cores including an amplifier device with three electrodes having two electrodes connected in said transfer loop to produce a transfer of signals of only one polarity through said loop, and a regenerative triggering circuit coupled with the amplifier device to cause the input one of said cores to switch from one binary state to another in response to triggering flux induced in said output core.

References Cited in the file of this patent Publication: Transistors as On-Off Switches in Saturable Core Circuits" by Bright, Pitman & Royer, which appeared in the Dec-ember, 1954, issue of Electrical Manufacturing," pp. 79-82.

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