GB1210803A - Improvements in or relating to oscillators - Google Patents

Abstract

1,210,803. Automatic control of frequency; superheterodyne radio receivers; pulse circuits. PLESSEY CO. Ltd. 6 March, 1968 [8 March, 1967], No. 11004/67. Headings H3A, H3P and H3Q. Drift of an oscillator is reduced by applying the oscillations for predetermined times to a device which provides one or other of two outputs in accordance with the number of cycles generated in the time, which outputs cause adjustment of the frequency towards the desired value in accordance with the predominant output. In Fig. 3, the output of oscillator 12 is periodically gated to a decimal counter 14 arranged so that if the last significant figure is 0 to 5 the counter produces a positive voltage and if 6 to 9 produces a negative voltage. This output is applied to an integrating capacitor so that if it is positive the capacitor voltage increases, decreasing the capacitance of a varicap diode connected thereto and thus increasing the frequency of the associated oscillator. The next or another subsequent count will therefore increase the six to nine range and the capacitor will then be connected to the negative voltage, discharging the capacitor and lowering the frequency. In this way the frequency will tend towards a value between the two counts. A ten position switch may provide for the sign of the output to changeover between other selected values of digits so that the frequency is stabilized at different values of the last significant figure. Alternately the stabilized fre quency can be varied by varying the number of the cycles gated to the counter as by varying the duration of the gating pulse from 18 (as described below). A bi-stable circuit may replace the counter (Fig. 1, not shown) and this will come to rest in one state for say an even number of cycles and in the other state for the odd number. Accordingly the frequency will tend to a value between a chosen even and odd number of cycles. The Fig. 3 circuit may be used as the local oscillator of a superheterodyne receiver by combining a switch selected sub-harmonic of the master oscillator 16 with the variable frequency from oscillator 12. The switch and a counter 21 controlled by a gate 22 can be so calibrated that they indicate respectively the whole number and decimal values of the frequency of the signal being received. To this end it may be necessary to offset the starting value of the counter 21. The pulse width varying circuit 18 receives regular pulses at its input and steers the leading and trailing edges to respective inputs of a bi-stable circuit 19 via delay circuits R1C1 and R2C2. Varying R2 thus controls the width of the output pulses of the bi-stable circuit. Temperature drift is minimized by making the delay circuit similar.