GB1193642A - Improvements in or relating to Matrix Storage Arrangements. - Google Patents

Improvements in or relating to Matrix Storage Arrangements.

Info

Publication number
GB1193642A
GB1193642A GB2935166A GB2935166A GB1193642A GB 1193642 A GB1193642 A GB 1193642A GB 2935166 A GB2935166 A GB 2935166A GB 2935166 A GB2935166 A GB 2935166A GB 1193642 A GB1193642 A GB 1193642A
Authority
GB
United Kingdom
Prior art keywords
address
gates
elements
signals
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2935166A
Inventor
Anthony Thomas Gibson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMI Ltd
Electrical and Musical Industries Ltd
Original Assignee
EMI Ltd
Electrical and Musical Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EMI Ltd, Electrical and Musical Industries Ltd filed Critical EMI Ltd
Priority to GB2935166A priority Critical patent/GB1193642A/en
Publication of GB1193642A publication Critical patent/GB1193642A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Recording Or Reproducing By Magnetic Means (AREA)

Abstract

1,193,642. Circuits employing bi-stable magnetic elements. ELECTRIC & MUSICAL INDUSTRIES Ltd. 28 June, 1967 [30 June, 1966], No. 29351/66. Heading H3B. A matrix storage arrangement includes delay elements in the output circuits in order to compensate for the delay imposed on address drive signals in reaching the different storage elements along an address conductor. In the word organized thin magnetic film store 1 information read out of the store by application of an address drive signal to a selected address row conductor is applied in parallel via read amplifiers 7 to gates 12 which are strobed by pulses from source 10 in order to suppress noise in the output conductors. Because of the finite time for the address drive signal to travel along an address conductor the output signals produced by the rotation of the magnetic vectors of the elements do not appear simultaneously and these signals appear at the gates 12 in echelon. In order that the strobing pulses arrive at the gates 12 at the required time, delay elements 11 are connected between the pulse source 10 and the gates. In order to write information into the elements appropriate drive signals are applied to the digit drive conductors also in echelon. These drive signals may be derived from the gates 12 which are already in echelon and overlap the address drive signals. In an alternative arrangement the sense conductors of the storage matrix may include different delays so that the output signals of the storage matrix appear simultaneously at the read amplifiers 7 and in this case delay elements 11 are omitted. Different delays may also be included in the digit drive conductors. Reference has been directed by the Comptroller to Specification 1,066,246.
GB2935166A 1966-06-30 1966-06-30 Improvements in or relating to Matrix Storage Arrangements. Expired GB1193642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB2935166A GB1193642A (en) 1966-06-30 1966-06-30 Improvements in or relating to Matrix Storage Arrangements.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2935166A GB1193642A (en) 1966-06-30 1966-06-30 Improvements in or relating to Matrix Storage Arrangements.

Publications (1)

Publication Number Publication Date
GB1193642A true GB1193642A (en) 1970-06-03

Family

ID=10290155

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2935166A Expired GB1193642A (en) 1966-06-30 1966-06-30 Improvements in or relating to Matrix Storage Arrangements.

Country Status (1)

Country Link
GB (1) GB1193642A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4223396A (en) * 1978-05-18 1980-09-16 Tokyo Shibaura Denki Kabushiki Kaisha Delayed line for sense amplifier pulse
US4556961A (en) * 1981-05-26 1985-12-03 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory with delay means to reduce peak currents

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4223396A (en) * 1978-05-18 1980-09-16 Tokyo Shibaura Denki Kabushiki Kaisha Delayed line for sense amplifier pulse
US4556961A (en) * 1981-05-26 1985-12-03 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory with delay means to reduce peak currents

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees