GB1161930A - Indicating Circuit - Google Patents

Indicating Circuit

Info

Publication number
GB1161930A
GB1161930A GB31745/67A GB3174567A GB1161930A GB 1161930 A GB1161930 A GB 1161930A GB 31745/67 A GB31745/67 A GB 31745/67A GB 3174567 A GB3174567 A GB 3174567A GB 1161930 A GB1161930 A GB 1161930A
Authority
GB
United Kingdom
Prior art keywords
register
latches
registers
nth
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB31745/67A
Inventor
Robert William Taylor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to GB31745/67A priority Critical patent/GB1161930A/en
Priority to FR1575940D priority patent/FR1575940A/fr
Priority to DE19681774514 priority patent/DE1774514C3/en
Priority claimed from DE19681774514 external-priority patent/DE1774514C3/en
Publication of GB1161930A publication Critical patent/GB1161930A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G06F12/125—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being generated by decoding an array or storage

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Digital Computer Display Output (AREA)
  • Executing Machine-Instructions (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

1,161,930. Data storage. INTERNATIONAL BUSINESS MACHINES CORP. 11 July, 1967, No. 31745/67. Heading G4C. The least recently accessed of a plurality of storage registers is indicated by a multi-input " indicator " respective to the register, accessing of a given register deactivating all inputs to the corresponding " indicator " and activating inputs of the " indicators" associated with other registers, simultaneous activation of all the inputs of a given indicator causing it to emit a " least recently accessed " signal for the respective register. In one embodiment, a 4 x 4 matrix of bietable latches lacking the leading diagonal is provided in the case of 4 registers. Access to the nth register resets all the latches in the nth row and sets all the latches in the nth column, so that the set state of the jth row, kth column latch indicates that the kth register has been accessed since the last access to the jth register. The set outputs of all the latches in a given row (say the nth) go to an AND gate which thus produces an output when the nth register is the least recently assessed. A second embodiment uses only half the matrix of latches by using the reset outputs of those retained as AND gate inputs in place of the set outputs of the corresponding latches deleted. In an application, an input address tag is associatively compared with tags stored one in each first register of four pairs of registers, a match causing the contents of the second register of the pair giving the match to be accessed and used to address a memory which may be of lower speed than the registers. The accessing operates the system of either of the two preceding paragraphs, which selects the least recently accessed register-pair to be loaded from the memory with a tag and address in the event that an input tag does not match any of the tags stored in the first registers of the register-pairs. A " register may store any number of words. Reference has been directed by the Comptroller to Specification 979,633.
GB31745/67A 1967-07-11 1967-07-11 Indicating Circuit Expired GB1161930A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB31745/67A GB1161930A (en) 1967-07-11 1967-07-11 Indicating Circuit
FR1575940D FR1575940A (en) 1967-07-11 1968-06-19
DE19681774514 DE1774514C3 (en) 1967-07-11 1968-07-05 Circuit arrangement for displaying a register

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB31745/67A GB1161930A (en) 1967-07-11 1967-07-11 Indicating Circuit
DE19681774514 DE1774514C3 (en) 1967-07-11 1968-07-05 Circuit arrangement for displaying a register

Publications (1)

Publication Number Publication Date
GB1161930A true GB1161930A (en) 1969-08-20

Family

ID=25755656

Family Applications (1)

Application Number Title Priority Date Filing Date
GB31745/67A Expired GB1161930A (en) 1967-07-11 1967-07-11 Indicating Circuit

Country Status (2)

Country Link
FR (1) FR1575940A (en)
GB (1) GB1161930A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0050919A2 (en) * 1980-10-27 1982-05-05 Control Data Corporation LRU resolving network apparatus
EP0309737A2 (en) * 1987-09-30 1989-04-05 Siemens Aktiengesellschaft System for creating an LRU-like mechanism for more than three terms by binary matrix trees
EP0309712A2 (en) * 1987-09-30 1989-04-05 Siemens Aktiengesellschaft System for creating an LRU-like mechanism for more than three terms by binary matrix trees

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1278220A (en) * 1971-03-13 1972-06-21 Ibm Indicating circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0050919A2 (en) * 1980-10-27 1982-05-05 Control Data Corporation LRU resolving network apparatus
EP0050919A3 (en) * 1980-10-27 1984-08-08 Control Data Corporation Lru resolving network apparatus
EP0309737A2 (en) * 1987-09-30 1989-04-05 Siemens Aktiengesellschaft System for creating an LRU-like mechanism for more than three terms by binary matrix trees
EP0309712A2 (en) * 1987-09-30 1989-04-05 Siemens Aktiengesellschaft System for creating an LRU-like mechanism for more than three terms by binary matrix trees
EP0309712A3 (en) * 1987-09-30 1990-06-20 Siemens Aktiengesellschaft System for creating an lru-like mechanism for more than three terms by binary matrix trees
EP0309737A3 (en) * 1987-09-30 1990-06-20 Siemens Aktiengesellschaft System for creating an lru-like mechanism for more than three terms by binary matrix trees

Also Published As

Publication number Publication date
DE1774514A1 (en) 1971-10-21
FR1575940A (en) 1969-07-25
DE1774514B2 (en) 1975-10-16

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Legal Events

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PS Patent sealed
PE Patent expired