GB1160058A - Method for Establishing During Manufacture Regions having Different Carrier Lifetimes in a Semiconductor Body - Google Patents

Method for Establishing During Manufacture Regions having Different Carrier Lifetimes in a Semiconductor Body

Info

Publication number
GB1160058A
GB1160058A GB17068/68A GB1706868A GB1160058A GB 1160058 A GB1160058 A GB 1160058A GB 17068/68 A GB17068/68 A GB 17068/68A GB 1706868 A GB1706868 A GB 1706868A GB 1160058 A GB1160058 A GB 1160058A
Authority
GB
United Kingdom
Prior art keywords
region
metal impurity
semi
gettering
during manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB17068/68A
Other languages
English (en)
Inventor
Israel Arnold Lesk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of GB1160058A publication Critical patent/GB1160058A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/904—Charge carrier lifetime control

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)
  • Bipolar Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
GB17068/68A 1967-04-26 1968-04-09 Method for Establishing During Manufacture Regions having Different Carrier Lifetimes in a Semiconductor Body Expired GB1160058A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US63383467A 1967-04-26 1967-04-26

Publications (1)

Publication Number Publication Date
GB1160058A true GB1160058A (en) 1969-07-30

Family

ID=24541308

Family Applications (1)

Application Number Title Priority Date Filing Date
GB17068/68A Expired GB1160058A (en) 1967-04-26 1968-04-09 Method for Establishing During Manufacture Regions having Different Carrier Lifetimes in a Semiconductor Body

Country Status (5)

Country Link
US (1) US3486950A (xx)
BE (1) BE714227A (xx)
DE (1) DE1764180B2 (xx)
FR (1) FR1570017A (xx)
GB (1) GB1160058A (xx)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2117861A1 (xx) * 1970-12-10 1972-07-28 Fmc Corp
JPS4826659B1 (xx) * 1969-11-15 1973-08-14

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3645808A (en) * 1967-07-31 1972-02-29 Hitachi Ltd Method for fabricating a semiconductor-integrated circuit
US3946425A (en) * 1969-03-12 1976-03-23 Hitachi, Ltd. Multi-emitter transistor having heavily doped N+ regions surrounding base region of transistors
US3640783A (en) * 1969-08-11 1972-02-08 Trw Semiconductors Inc Semiconductor devices with diffused platinum
US3860947A (en) * 1970-03-19 1975-01-14 Hiroshi Gamo Thyristor with gold doping profile
US3727116A (en) * 1970-05-05 1973-04-10 Rca Corp Integral thyristor-rectifier device
US3838440A (en) * 1972-10-06 1974-09-24 Fairchild Camera Instr Co A monolithic mos/bipolar integrated circuit structure
JPS5942989B2 (ja) * 1977-01-24 1984-10-18 株式会社日立製作所 高耐圧半導体素子およびその製造方法
US4140560A (en) * 1977-06-20 1979-02-20 International Rectifier Corporation Process for manufacture of fast recovery diodes
DE3037316C2 (de) * 1979-10-03 1982-12-23 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Verfahren zur Herstellung von Leistungsthyristoren
IT1245365B (it) * 1991-03-28 1994-09-20 Cons Ric Microelettronica Struttura integrata di dispositivo bipolare di potenza ad elevata densita' di corrente e diodo veloce e relativo processo di fabbricazione
DE10324100B4 (de) * 2003-05-27 2008-09-25 Infineon Technologies Ag Verfahren zur Herstellung eines robusten Halbleiterbauelements
DE102007020039B4 (de) * 2007-04-27 2011-07-14 Infineon Technologies Austria Ag Verfahren zur Herstellung einer vertikal inhomogenen Platin- oder Goldverteilung in einem Halbleitersubstrat und in einem Halbleiterbauelement, derart hergestelltes Halbleitersubstrat und Halbleiterbauelement

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3440113A (en) * 1966-09-19 1969-04-22 Westinghouse Electric Corp Process for diffusing gold into semiconductor material
US3440114A (en) * 1966-10-31 1969-04-22 Texas Instruments Inc Selective gold doping for high resistivity regions in silicon

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4826659B1 (xx) * 1969-11-15 1973-08-14
FR2117861A1 (xx) * 1970-12-10 1972-07-28 Fmc Corp

Also Published As

Publication number Publication date
BE714227A (xx) 1968-10-25
FR1570017A (xx) 1969-06-06
DE1764180A1 (de) 1971-04-15
DE1764180B2 (de) 1972-02-10
US3486950A (en) 1969-12-30

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees