GB1149072A - Improvements in or relating to time-division signal connecting and branching systems - Google Patents

Abstract

1,149,072. Multiplex pulse signalling. FUJITSU Ltd. 20 April, 1966 [20 April, 1965], No. 17380/66. Heading H4L. In an arrangement for inserting relatively low speed signals in vacant time slots and dropping off low speed signals in a time division multiplex system, means are provided for comparing the timing of the pulses of the t.d.m. signal and that of the pulses to be inserted and generating a control signal for controlling the timing of the pulses to be inserted. The system is described in relation to P.C.M. signals but is stated to be suitable for time division signals in general. Signals passing from C, conductor 3, to B, terminal 4, are to be inserted in vacant time slots in t.d.m. signals passing from A, terminal 2, to B, terminal 4, these vacant slots occurring at a frequency equal to the repetition frequency of the signals to be inserted, and signals from B, terminal 5 to C, conductor 7, are to be extracted from the t.d.m. signals passing from B, terminal 5, to A, terminal 6. A timing circuit 16 provides a pulse at 17 on the occurence of a vacant time slot which is compared in phase detector 9 with the signal appearing on conductor 3 to generate a control signal on conductor 10 which indicates the difference in timing between the two signals, the control signal being positive or negative according to whether the error is in the forward or backward direction. The signals to be dropped off are selected by a timing circuit 18 and supplied via an AND gate 19A to a pulse shaper 20, and transmitted via an OR gate 22B to the decoder at the receiver terminal 14. The output of shaper 20 also controls a timing circuit 21 operating at the frame repetition frequency of the low speed signals whose output is supplied to gate the output of phase detector 9 via an AND gate 22A and OR gate 22B to a timing circuit 23. By this means a control pulse is inserted at the end of a frame of the received low speed signals, Fig. 4 (not shown), and is supplied via conductor 15 to a phase control circuit 25, 26 at transmitter 13 which controls the pulse timing of the signals applied at 3 and supplied to conductor 4 via AND gate 8A and OR gate 8B.