GB1401436A - Pulse transmission systems - Google Patents

Abstract

1401436 Digital transmission; signalling by DC GENERAL ELECTRIC CO Ltd 20 Dec 1972 [14 Oct 1971] 47884/71 Heading H4P A transmission path carrying data in both directions during a similar period has pulses transmitted from a second terminal only during gaps between adjacent pulses received from a first terminal, each terminal having inhibiting means for substantially preventing pulses from a transmitting terminal from being detected by a receiver at that terminal. In the embodiment described the first terminal is a master and the second terminal a slave. Preferably timing pulses are issued by the master and controlled by a clock which pulses are regenerated at the slave, conveniently by a phase locked loop. The total delay of the transmission path may be arranged to be an integral number of half periods of bit frequency which ensures that incoming pulses from the slave fall into gaps from the master hence will not be suppressed by gating means at that terminal. If the path delay is not an exact multiple, incoming pulses may coincide with transmitted pulses hence may be suppressed; this may be overcome by making incoming pulses of greater duration than outgoing pulses. A further method is to insert a fixed delay of “ operating period or alternatively transmit from the slave terminal double pulses spaced ¢ period apart at least one of which will be unsuppressed. Master terminal 2 receives binary input through pulse shaper 4 and transmits through line driver 5 binary or bipolar signals of period To determined by master clock 6 of duration shorter than To determined by pulse shaper 4. At slave 3, pulses are fed through gates 10 which allows pulses only to pass to amplifier 11 during periods t2 hence outgoing data through pulse shaper 7 and driver 8 is prevented from reaching amplifier 11. Output of 11 is applied to one input terminal of phase detector 12 the other input of which is supplied with a reference signal from oscillator 9 via 90 degree phase shift 13. Detector circuit 12 compares rising edge of reference waveform with centre of incoming pulses; if on either side of centre oscillator frequency adjustment is made. As a result pulses transmitted by a slave 3 are interleaved with incoming pulses from master 2. Incoming pulses are sampled by circuit 14 and samples above a threshold pass forward. At the master station incoming pulses pass through gate 15 controlled by clock 6 to prevent driver pulses reaching amplifier 16. The clock regeneration circuit may be similar to circuit 20. Incoming and outgoing pulses will be correctly interleaved if transmission delay is equal to an integral number of half periods of clock frequency which is ensured by a variable delay element 19. Where a fixed delay is employed, incoming pulses are taken from either before or after the delay element dependent on which point gives better degree of interleave.