GB1114497A - Improvements in or relating to semiconductor devices - Google Patents

Improvements in or relating to semiconductor devices

Info

Publication number
GB1114497A
GB1114497A GB705866A GB705866A GB1114497A GB 1114497 A GB1114497 A GB 1114497A GB 705866 A GB705866 A GB 705866A GB 705866 A GB705866 A GB 705866A GB 1114497 A GB1114497 A GB 1114497A
Authority
GB
United Kingdom
Prior art keywords
silicon
bonding pads
substrate
connections
thermally
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB705866A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dow Silicones Corp
Original Assignee
Dow Corning Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dow Corning Corp filed Critical Dow Corning Corp
Publication of GB1114497A publication Critical patent/GB1114497A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature

Abstract

1,114,497. Integral circuits; circuit assemblies. DOW CORNING CORPORATION. 17 Feb., 1966 [28 June, 19651, No. 7058/66. Headings H1K and H1R. Semi-conductor devices such as diodes and transistors are formed in islands of silicon embedded in an electrically insulating but thermally conductive substrate of silicon carbide. External connections are thermocompression bonded to metal deposits extending to relatively large silicon bonding pads also embedded in the substrate but thermally insulated therefrom by a silicon oxide layer. The concept is illustrated by a structure which is made by photo-resist masking and etching a silicon wafer to leave mesas 12, 14, 13 which are to form bonding areas and a device. The mesacontaining surface is then thermally or steam oxidized to form an oxide coating 15 which is then selectively removed from the mesa in which a device is to be formed. Silicon carbide is deposited by decomposition of methylcontaining chlorosilanes to form a substrate 16, and the base portion of the silicon wafer is lapped and/or etched away to leave the mesa portions as islands in the substrate. An active device is formed in region 13 by planar techniques; any necessary inductors, capacitors, resistors, or insulating layers and the connections to the bonding pads are formed by thin film techniques; and the external leads are individually thermocompression bonded to the connections at the bonding pads, heat transmission to the other bonding pads (and to the active device) being prevented by the presence of the oxide layer 15.
GB705866A 1965-06-28 1966-02-17 Improvements in or relating to semiconductor devices Expired GB1114497A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US46753965A 1965-06-28 1965-06-28

Publications (1)

Publication Number Publication Date
GB1114497A true GB1114497A (en) 1968-05-22

Family

ID=23856107

Family Applications (1)

Application Number Title Priority Date Filing Date
GB705866A Expired GB1114497A (en) 1965-06-28 1966-02-17 Improvements in or relating to semiconductor devices

Country Status (1)

Country Link
GB (1) GB1114497A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2507353A1 (en) * 1981-06-05 1982-12-10 Cepe THERMAL COUPLING CELL BETWEEN A HEAT ELEMENT AND A THERMO-SENSITIVE ELEMENT AND THERMOSTATED ENCLOSURE FOR PIEZOELECTRIC CRYSTAL COMPRISING SUCH A CELL
WO2003036699A2 (en) * 2001-10-23 2003-05-01 Cambridge Semiconductor Limited Lateral semiconductor-on-insulator structure and corresponding manufacturing methods

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2507353A1 (en) * 1981-06-05 1982-12-10 Cepe THERMAL COUPLING CELL BETWEEN A HEAT ELEMENT AND A THERMO-SENSITIVE ELEMENT AND THERMOSTATED ENCLOSURE FOR PIEZOELECTRIC CRYSTAL COMPRISING SUCH A CELL
EP0067752A1 (en) * 1981-06-05 1982-12-22 Compagnie D'electronique Et De Piezo-Electricite - C.E.P.E. Thermal coupling cell and temperature-regulated space using such a cell
WO2003036699A2 (en) * 2001-10-23 2003-05-01 Cambridge Semiconductor Limited Lateral semiconductor-on-insulator structure and corresponding manufacturing methods
WO2003036699A3 (en) * 2001-10-23 2003-09-25 Cambridge Semiconductor Ltd Lateral semiconductor-on-insulator structure and corresponding manufacturing methods

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