GB1078971A - Improvements in or relating to signalling systems - Google Patents

Abstract

1,078,971. Telegraphy. GENERAL ELECTRIC CO. Ltd., and W. J. BATTELL. Jan. 30, 1964 [Oct. 30, 1962], No. 41099/62. Heading H4P. [Also in Division G4] Single errors in the transmission of 5-bit characters are corrected by generating five check bits for each character before transmission, re-calculating these check bits from the received character, and comparing the received and re-calculated check bits to derive correction signals. If a character is represented by bits V 1 -V 5 then the check bits V 6 -V 10 are calculated from the expressions:- the sum being mod 2 in each case. This is done by use of a trigger which is switched by each binary 1 received to generate #V j , and a mod 2 adder (exclusive OR gate) supplied with signals from the trigger and a circulating register containing V 1-5 . Figure 2 shows the correction arrangement, including a similar trigger 18 counting the received character bits V<SP>1</SP> 1 -V<SP>1</SP> 5 which are fed to circulating register 20. Switch 17 is then changed over and 22, 24 and 25 closed so that V<SP>1</SP> 6 - V<SP>1</SP> 10 are calculated by mod 2 adder 23 and added to the received check bits at 28. Any inequality causes a "1" to be entered into shift register 29 and it is shown that these 1's represent the inverse of the desired corrections for V<SP>1</SP> 1 - V<SP>1</SP> 5 in the correct order, provided that a single transmission error only has occurred. They are thus fed (in inverted form) from the output of 29 to modulo 2 adder 31 provided that the counter 30 has received the number of 1's corresponding to a single error; if more than one error is detected all output is inhibited at 33.