1,078,483. Multiplex pulse code signalling. SOCIETA ITALIANA TELECOMUNICAZIONI SIEMENS S.p.A. March 23, 1965 [March 24, 1964], No. 12178/65. Heading H4L. A telephone transmission system comprises a number n of talking lines, signals in a number, m<n, active ones of which are sampled and coded for transmission in time multiplex. The frame of coded samples is preceded by a distributing message in order to ensure that the coded signals are correctly directed to the respective talking lines at the remote terminal. All talking lines are sampled simultaneously in transmission, unless the line is being sampled in reception, but the coding of any line which remains idle for a predetermined length of time is terminated so that the total number of lines coded in each frame does not exceed the predetermined number m, in the preferred n embodiment m=-. Fig. 1 shows an embodi- 2 ment in which lines 1LN to nLN are connected to transmit capacitor stores, MCe1 to MCen, or receive capacitor stores, MCr1 to MCrn, simultaneously once per frame. Those transmit stores which have signals above a predetermined level are connected to a p.c.m. coder by gates PC1 to PCn which are operated cyclically by a stepping switch CDe1 to CDen various stages of which may be omitted by operation of switches CEe1 to CEen in accordance with information, stored in the memory Me1 to Men, as to which of lines LN are active. The arrangement is such that the memory stages Me1-Men set switches CEe1-CEen to bypass stepping switch stages CDe1-CDen corresponding to inactive lines. At the same time the memory stages ME1- MEn set switches CE1-CEn in a complementary condition so as to bypass those stages of a second stepping counter CP1-CPn associated with active ones of the lines. During each complete multiplex frame period, a group of n pulses is transmitted each pulse corresponding to one talking line and of a characteristic value, e.g. positive or negative, according as the respective line is active or inactive. These pulses are derived from the outputs i1, i2 . . . in of the memory stages Me1-Men. Following this distributing message, in the same order, are transmitted the p.c.m. groups corresponding to the signals on the active lines, switched sequentially by the stages CDe1-CDen, m groups being allotted for this information. Comparison gates CT1-CTn are enabled in turn by the outputs of those stages CDel-CDen corresponding to active lines, a further input to these gates is provided by the level control circuit SG, which is connected to the line to the input of the p.c.m. coder, and gives an output whenever the signal on the line corresponds to a signal from an active line. The comparison gates provide one input to "and" gates EL1-ELn the other input to which is derived from the last stage of the stepping switch so that after all the p.c.m. groups have been transmitted a signal is transmitted only through those gates corresponding to lines still active, which signal serves to reset the corresponding ones of memory stages Mel-Men so that the corresponding lines will be sampled in the next frame, while those lines which have become idle will not be sampled in the next frame. When all the active lines have been sampled and assuming that the number of active lines is smaller than the number m of channels allotted in the transmission, the stepping switch stage CDen passes a pulse to open gate A which in turn causes gate B to feed the remaining pulses of the frame to the second stepping counter CP1-CPn this causes some of the lines which were previously idle to be sampled to ascertain whether they are still idle, if they are not the corresponding memory stages Mel-Men are operated so that these lines will be sampled during the following frame. At the end of the frame the stepping counter position is frozen so that at the end of the following frame the counter continues stepping to ascertain the condition of lines not sampled on the previous frame. All the lines are therefore sampled over a succession of frames, except those locked out by the receiver portion of the equipment. Received signals are preceded by the distributing message which is demultiplexed and fed via lines h1; h2, . . . hn to a receive memory Mr1-Mrn which in turn sets switches CEr1-CErn to bypass those stepping switch stages corresponding to lines on which no signal is incoming from the p.c.m. decoder. The decoded signals on line f are switched through respective switches PM1- PMn to the capacitor stores MCr1-MCrn in the appropriate sequency and at the end of the frame sampling switches. PCAr1-PCArn are operated simultaneously to feed the stored samples into the lines 1LN to nLN. The receive memory and the transmit sampling gates are interconnected as is the transmit memory and receive sampling gates so that a line which is in use in the transmission of signals cannot be used for the reception and vice versa, this system obviating the use of hybrid transformers or other echo suppressors.