GB1072929A - Synchronization system for p.c.m. transmission - Google Patents

Synchronization system for p.c.m. transmission

Info

Publication number
GB1072929A
GB1072929A GB49808/63A GB4980863A GB1072929A GB 1072929 A GB1072929 A GB 1072929A GB 49808/63 A GB49808/63 A GB 49808/63A GB 4980863 A GB4980863 A GB 4980863A GB 1072929 A GB1072929 A GB 1072929A
Authority
GB
United Kingdom
Prior art keywords
delay line
output
signals
delay
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB49808/63A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP37055802A external-priority patent/JPS4917885B1/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1072929A publication Critical patent/GB1072929A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/062Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)

Abstract

1,072,929. Multiplex pulse code signalling. HITACHI SEISAKUSHO KABUSHIKI KAISHA. Dec. 17, 1963 [Dec. 18, 1962 (2)], No. 49808/63. Heading H4L. Two time division multiplex pulse code modulation systems, each having independent timing circuits, are interconnected by the use of an automatically adjustable delay means, the delay being continuously adjusted and one frame being periodically repeated or missed according to the relationship between the two frequencies. In one arrangement, Fig. 4, a magnetostrictive delay line MD is provided with an input circuit W receiving signals S B from a remote station B, and two output circuits R 1 R 2 , the circuit W being movable along the delay line under the control of a comparator S c receiving framing signal F Ba selected at F D from the output S Ba at terminal 42, and the locally generated framing signals F A . An electronic switch SW selects via gate G 1 or G 2 which output R 1 or R 2 is in use by switching over the output when the circuit W reaches point P 1 or P 2 . The length of the delay line is such that the signals obtained from R 1 and R 2 differ by one frame. An ultrasonic delay line which may be of circular or semicircular form may be used. In the case of the parallel transmission of p.c.m. signals an adjustable delay line is provided for each of the parallel channels, the delay lines being controlled by a common adjusting means.
GB49808/63A 1962-12-18 1963-12-17 Synchronization system for p.c.m. transmission Expired GB1072929A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5580162 1962-12-18
JP37055802A JPS4917885B1 (en) 1962-12-18 1962-12-18

Publications (1)

Publication Number Publication Date
GB1072929A true GB1072929A (en) 1967-06-21

Family

ID=26396713

Family Applications (1)

Application Number Title Priority Date Filing Date
GB49808/63A Expired GB1072929A (en) 1962-12-18 1963-12-17 Synchronization system for p.c.m. transmission

Country Status (2)

Country Link
FR (1) FR1378474A (en)
GB (1) GB1072929A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2206268A (en) * 1987-06-25 1988-12-29 Racal Data Communications Inc Sampling clock synchronisation

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2206268A (en) * 1987-06-25 1988-12-29 Racal Data Communications Inc Sampling clock synchronisation
US4815109A (en) * 1987-06-25 1989-03-21 Racal Data Communications Inc. Sampling clock synchronization
GB2206268B (en) * 1987-06-25 1991-08-07 Racal Data Communications Inc Sampling clock synchronisation

Also Published As

Publication number Publication date
FR1378474A (en) 1964-11-13

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