GB1061060A - Semiconductor structure and method - Google Patents

Semiconductor structure and method

Info

Publication number
GB1061060A
GB1061060A GB38280/64A GB3828064A GB1061060A GB 1061060 A GB1061060 A GB 1061060A GB 38280/64 A GB38280/64 A GB 38280/64A GB 3828064 A GB3828064 A GB 3828064A GB 1061060 A GB1061060 A GB 1061060A
Authority
GB
United Kingdom
Prior art keywords
wafer
layer
support
islands
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB38280/64A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Signetics Corp
Original Assignee
Signetics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Signetics Corp filed Critical Signetics Corp
Publication of GB1061060A publication Critical patent/GB1061060A/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)

Abstract

1,061,060. Semi - conductor devices. SIGNETICS CORPORATION. Sept. 18, 1964 [Dec. 16, 1963; Jan. 20, 1964], No. 38280/64. Heading HlK. An integrated circuit structure comprises a plurality of semi-conductor bodies disposed in recesses in a support member coated with insulating material. A typical arrangement may be made from a monocrystalline silicon wafer by oxidizing its surface and then forming grooves in it defining isolated mesas, using photolithographic techniques. The oxide layer is reformed in the grooves and a thick mass of insulating material, later to form a support, vapour deposited on the grooved face. Material ' is then etched or lapped from the opposite face of the wafer down to the oxide in the groove bottoms to leave islands in which diodes or transistors may be formed by conventional masking and diffusion techniques. These may be interconnected. Fig. 9, by conductive tracks and passive components such as resistors formed by evaporation on an oxide layer which, if the support layer is polycrystalline silicon, may extend over the whole of the lapped face. A layer of opposite conductivity type at the base of each island can be provided simply by forming such a layer on the wafer at the start of the process. To accurately control the thickness of the islands the edges of the deposited support may be etched away before mounting it in a recess 39 of a lapping machine, Fig. 12 (not shown). Lapping is terminated by diamond stops 42. Alternatively the wafer edges are removed to leave shoulders on the support which are then coated with chromium. In this case lapping terminates when the lapping face contacts the hard chromium. If the support is of a hard material, e.g. alumina or silicon carbide. it may itself act as a stop. In a further modification shoulders are formed on the wafer at the same time as the grooves and the chromium stop layer deposited there before depositing the support. In other methods the semi-conductor portions are separated before the final support layer is deposited. Thus, as described with reference to Figs. 20-24 (not. shown), a plain superficially oxidized wafer has polycrystalline silicon deposited on it. The wafer is then etched using photolithographic techniques to form a series of islands which are re-oxidized. A second polycrystalline layer is deposited between and on the exposed faces of the islands and the first layer removed to leave the-assembly of Fig. 24. In a modification of this the wafer is machined down to stops as previously described before forming the islands. A similar technique may also be performed on a sub-assembly made by forming a layer of opposite conductivity type on one wafer face by diffusion or epitaxial deposition before oxidizing. After deposition of the support on the treated wafer face the wafer is electrolytically etched down to the layer, from which the islands are then formed. Another way of treating the PN wafer is to etch away sections of the layer to leave isolated portions. After re-oxidizing and depositing support material over and between these portions the wafer material is removed down to the layer to complete the isolation. Formation of device structures in isolated sections is preferably done after isolation but it is possible to form them before. This is essential where such structures are to be formed on both faces of the islands as in Fig. 60 (not shown). In this case the buried junctions are formed in the base wafer at the outset while the others are formed by diffusion into the completed structure. In this particular arrangement support 22 is conductive and contacts zones of the device: structures through apertures in the oxide.
GB38280/64A 1963-12-16 1964-09-18 Semiconductor structure and method Expired GB1061060A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US33069763A 1963-12-16 1963-12-16
US33880264A 1964-01-20 1964-01-20

Publications (1)

Publication Number Publication Date
GB1061060A true GB1061060A (en) 1967-03-08

Family

ID=26987403

Family Applications (1)

Application Number Title Priority Date Filing Date
GB38280/64A Expired GB1061060A (en) 1963-12-16 1964-09-18 Semiconductor structure and method

Country Status (6)

Country Link
BE (1) BE657077A (en)
CA (1) CA952628A (en)
DE (1) DE1439485A1 (en)
FR (1) FR1421618A (en)
GB (1) GB1061060A (en)
NL (1) NL6411895A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1439760B2 (en) * 1964-12-19 1976-06-24 Telefunken Patentverwertungsgesellschaft Mbh, 7900 Ulm TRANSISTOR AND PROCESS FOR ITS MANUFACTURING
NL7001607A (en) * 1970-02-05 1971-08-09
US3954522A (en) * 1973-06-28 1976-05-04 Motorola, Inc. Integrated circuit process
US3875413A (en) * 1973-10-09 1975-04-01 Hewlett Packard Co Infrared radiation source

Also Published As

Publication number Publication date
DE1439485A1 (en) 1968-11-28
CA952628A (en) 1974-08-06
NL6411895A (en) 1965-06-17
FR1421618A (en) 1965-12-17
BE657077A (en) 1965-04-01

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