GB1057381A - Improved means for address-selection of devices - Google Patents

Abstract

1,057,381. Automatic exchange systems. SIEMENS & HALSKE A.G. Aug. 13, 1963 [Aug. 16, 1962], No. 31944/63. Heading H4K. [Also in Division G4] A number of devices in a multi co-ordinate array may be selected simultaneously provided that the addresses of the devices to be selected do not differ by more than one word. Thus in a telephone system comprising a plurality of selector frames Z1 to Z3 each consisting of a number of cross-coil switches x, y, to x 4 Y 4 and a central store W into storage sections BW of which are placed three word addresses of switches to be operated, the sections BW are cyclically scanned and their contents are readout and placed into intermediate store H as long as each address differs from the previous one or ones in only one word. In respect of the first address the store H energizes one out of each of the three sets of relays X, Y, Z in order that the corresponding cross-coil switch may be selected. If it is assumed that the succeeding addresses differ only in the word corresponding to co-ordinate Z then the store H successively energizes the corresponding Z relays. The response time of the relays X, Y, Z and the cross-coil switches is much longer than that of the sampling time for any one of the storage sections BW so that in effect a plurality of cross-coil switches are operated simultaneously. Consequently the selection time is materially reduced without increasing the possibility of a false connection due to multiple marking. The words are written in binary 1 out of n code e.g. the word for selecting a Z relay is a " one bit " in one of the three possible positions for the bits. The comparators Vx, Vy, Vz compare the address(es) already in store H with the next one in the output register ZW of the store section BW. Provided one of the AND gates Kxy, Kyz, Kxz conducts thereby indicating coincidence of words in two of the comparators, inhibit gate 1G is blocked and the new address can be written into store H. If there is no coincidence, an output from the Z portion of store H is passed via OR gate M and gate 1G to the blocking inputs of gates G1 to G11. Store H can hold up to four addresses differing only in the X or Y word or up to three addresses for differences only in the Z word. Counter Q or timer T automatically inhibit further input to H when the latter is full, The store H may comprise monostable or bi stable circuits. The devices in the array may be magnetic ring cores.