GB1044972A - A synchronising device for a pulse communication receiver - Google Patents

Abstract

1,044,972. Multiplex pulse code signalling. NIPPON ELECTRIC CO. Ltd. April 25, 1963 [April 25, 1962], No. 16314/63. Heading H4L. A pulse transmission system is provided with " flywheel " synchronization at the receiver so that interference of short duration has no effect. Means for searching for and locking on to the correct synchronizing signal also are provided. As shown in Fig. 1, an incoming P.C.M. time division multiplex signal is supplied via terminal 21 to an output terminal 29 and also to a bit frequency filter 41 for deriving bit synchronizing signals, a bit-frequency filter 31 in a signal monitoring circuit 23, and an error pulse deriving circuit 53 in a frame synchronizing circuit 26. The bit frequency component from filter 41 is supplied to a phase comparator 43 together with the output of an oscillator 42 controlling the demodulating circuits, and the output of the phase comparator via a control signal store 44 and variable reactance 45 controls the oscillator 42. The filter 31 supplies a discriminator-amplifier circuit 32, Fig. 2 (not shown), for producing a predetermined D.C. output if the extracted bit frequency is normal so that a relay 33 is normally operated and a contact (not shown) in the control signal store 44 is closed, this contact when open causing the store to memorize the phase information for a time T1 on the occurrence of a fault. The relay is arranged to release after a delay t 1 after detection of an interruption in the incoming signal and to operate after a delay t 2 after the signal returns to normal. The time T1 is made much longer than the releasing time t 1 and longer than the anticipated failure time so that bit synchronism is maintained during the period T1. The frame synchronizing device 26 comprises a circuit 51 supplied with " error " pulses e from a circuit 54 which block bit timing pulses supplied from the oscillator 42 when pulses of the two trains are coincident, the output of the circuit 51 controlling a channel distributor 52. Assuming there are n channels, the n/2<SP>th</SP> and the n<SP>th</SP> output from the distributor are supplied to the error pulse circuit 53 which supplies an " interim error pulse train " e<SP>1</SP> only when frame synchronism has collapsed. The pulse train e<SP>1</SP> is supplied to the circuit 54 which is controlled by a switch contact (not shown) of the relay 33 so that error pulses e are only derived after a delay T f (frame synchronization waiting time) if pulses e<SP>1</SP> are still present. Each pulse e causes the distributor 52 to be shifted by one position for restoration of synchronism. A delay Tp is also introduced after detection of correct synchronization before normal operation is resumed.