GB1038704A - A self-addressed data store - Google Patents
A self-addressed data storeInfo
- Publication number
- GB1038704A GB1038704A GB627364A GB627364A GB1038704A GB 1038704 A GB1038704 A GB 1038704A GB 627364 A GB627364 A GB 627364A GB 627364 A GB627364 A GB 627364A GB 1038704 A GB1038704 A GB 1038704A
- Authority
- GB
- United Kingdom
- Prior art keywords
- bit
- word
- store
- address
- latches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
- G06F7/495—Adding; Subtracting in digit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/264—Microinstruction selection based on results of processing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Quality & Reliability (AREA)
- Computing Systems (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB627364A GB1038704A (en) | 1964-02-14 | 1964-02-14 | A self-addressed data store |
NL6501038A NL6501038A (enrdf_load_stackoverflow) | 1964-02-14 | 1965-01-28 | |
FR5146A FR1424317A (fr) | 1964-02-14 | 1965-02-11 | Contrôle de parité dans une mémoire de données à adressage automatique |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB627364A GB1038704A (en) | 1964-02-14 | 1964-02-14 | A self-addressed data store |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1038704A true GB1038704A (en) | 1966-08-10 |
Family
ID=9811523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB627364A Expired GB1038704A (en) | 1964-02-14 | 1964-02-14 | A self-addressed data store |
Country Status (2)
Country | Link |
---|---|
GB (1) | GB1038704A (enrdf_load_stackoverflow) |
NL (1) | NL6501038A (enrdf_load_stackoverflow) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2319938A1 (fr) * | 1975-07-30 | 1977-02-25 | Bodenseewerk Geraetetech | Installation pour la surveillance d' |
FR2337374A1 (fr) * | 1975-12-29 | 1977-07-29 | Honeywell Inf Systems | Systeme et procede de verification de memoire de commande |
FR2346770A1 (fr) * | 1976-03-30 | 1977-10-28 | Honeywell Inf Systems Italia | Appareil de commande microprogramme muni de moyens pour verifier l'adressage de la memoire de microprogrammation |
EP0098539A3 (de) * | 1982-07-03 | 1986-06-11 | Paul Merkle | Serielles Tetraden-Addier-Subtrahierwerk im BCD-8421-Code |
WO1989002125A1 (en) * | 1987-08-31 | 1989-03-09 | Unisys Corporation | Error detection system for instruction address sequencing |
US5241547A (en) * | 1987-08-31 | 1993-08-31 | Unisys Corporation | Enhanced error detection scheme for instruction address sequencing of control store structure |
-
1964
- 1964-02-14 GB GB627364A patent/GB1038704A/en not_active Expired
-
1965
- 1965-01-28 NL NL6501038A patent/NL6501038A/xx unknown
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2319938A1 (fr) * | 1975-07-30 | 1977-02-25 | Bodenseewerk Geraetetech | Installation pour la surveillance d' |
FR2337374A1 (fr) * | 1975-12-29 | 1977-07-29 | Honeywell Inf Systems | Systeme et procede de verification de memoire de commande |
FR2346770A1 (fr) * | 1976-03-30 | 1977-10-28 | Honeywell Inf Systems Italia | Appareil de commande microprogramme muni de moyens pour verifier l'adressage de la memoire de microprogrammation |
EP0098539A3 (de) * | 1982-07-03 | 1986-06-11 | Paul Merkle | Serielles Tetraden-Addier-Subtrahierwerk im BCD-8421-Code |
WO1989002125A1 (en) * | 1987-08-31 | 1989-03-09 | Unisys Corporation | Error detection system for instruction address sequencing |
US5241547A (en) * | 1987-08-31 | 1993-08-31 | Unisys Corporation | Enhanced error detection scheme for instruction address sequencing of control store structure |
Also Published As
Publication number | Publication date |
---|---|
NL6501038A (enrdf_load_stackoverflow) | 1965-08-16 |
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