GB0212260D0 - System wakeup - Google Patents

System wakeup

Info

Publication number
GB0212260D0
GB0212260D0 GBGB0212260.4A GB0212260A GB0212260D0 GB 0212260 D0 GB0212260 D0 GB 0212260D0 GB 0212260 A GB0212260 A GB 0212260A GB 0212260 D0 GB0212260 D0 GB 0212260D0
Authority
GB
United Kingdom
Prior art keywords
processor system
processor
components
activated
wake
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
GBGB0212260.4A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sendo International Ltd
Original Assignee
Sendo International Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sendo International Ltd filed Critical Sendo International Ltd
Priority to GBGB0212260.4A priority Critical patent/GB0212260D0/en
Priority to GB0214098A priority patent/GB2382180B/en
Publication of GB0212260D0 publication Critical patent/GB0212260D0/en
Priority to AU2003236890A priority patent/AU2003236890A1/en
Priority to PCT/GB2003/002274 priority patent/WO2003100632A2/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4405—Initialisation of multiprocessor systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • H04W52/0287—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
    • H04W52/0293—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

A method of waking up components in a dual-processor based system. The system includes a first processor system to be activated. Upon activation, components in a second processor based system are required to be likewise activated. The method comprises initiating a wake-up process of a first processor system, waking-up the first processor system components, and generating an interrupt signal. The interrupt signal is passed to the second processor system to initiate a wake-up process of the second processor system components that are required to be woken for the wake-up process of the first processor system. This is performed such that the second processor system components are activated at, or before, a time when the first processor system requires second processor system components to be activated. A dual processor based system is also described. In this manner, components used in a second processor system, for example a man machine processor system, are awoken in a timely manner when they are needed in the awakening process of the first processor system, for example a GSM processor system to facilitate the periodic scanning of a GSM control channel or timeslots. This prevents delay and reduces power consumption.
GBGB0212260.4A 2002-05-28 2002-05-28 System wakeup Ceased GB0212260D0 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GBGB0212260.4A GB0212260D0 (en) 2002-05-28 2002-05-28 System wakeup
GB0214098A GB2382180B (en) 2002-05-28 2002-06-19 Processor system wake-up
AU2003236890A AU2003236890A1 (en) 2002-05-28 2003-05-27 Dual-processor based system and method of waking up components therein
PCT/GB2003/002274 WO2003100632A2 (en) 2002-05-28 2003-05-27 Dual-processor based system and method of waking up components therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB0212260.4A GB0212260D0 (en) 2002-05-28 2002-05-28 System wakeup

Publications (1)

Publication Number Publication Date
GB0212260D0 true GB0212260D0 (en) 2002-07-10

Family

ID=9937557

Family Applications (2)

Application Number Title Priority Date Filing Date
GBGB0212260.4A Ceased GB0212260D0 (en) 2002-05-28 2002-05-28 System wakeup
GB0214098A Expired - Lifetime GB2382180B (en) 2002-05-28 2002-06-19 Processor system wake-up

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB0214098A Expired - Lifetime GB2382180B (en) 2002-05-28 2002-06-19 Processor system wake-up

Country Status (1)

Country Link
GB (2) GB0212260D0 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7493435B2 (en) * 2003-10-06 2009-02-17 Intel Corporation Optimization of SMI handling and initialization
WO2007081218A1 (en) * 2006-01-10 2007-07-19 Cupp Computing As Dual mode power-saving computing system
US8615647B2 (en) 2008-02-29 2013-12-24 Intel Corporation Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60230261A (en) * 1984-04-28 1985-11-15 Toshiba Corp Initializing control system in multi-processor system
US6158000A (en) * 1998-09-18 2000-12-05 Compaq Computer Corporation Shared memory initialization method for system having multiple processor capability

Also Published As

Publication number Publication date
GB0214098D0 (en) 2002-07-31
GB2382180B (en) 2003-10-22
GB2382180A (en) 2003-05-21

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Legal Events

Date Code Title Description
AT Applications terminated before publication under section 16(1)