GB0002249D0 - Data receiving circuit and clock recovery therein - Google Patents

Data receiving circuit and clock recovery therein

Info

Publication number
GB0002249D0
GB0002249D0 GB0002249A GB0002249A GB0002249D0 GB 0002249 D0 GB0002249 D0 GB 0002249D0 GB 0002249 A GB0002249 A GB 0002249A GB 0002249 A GB0002249 A GB 0002249A GB 0002249 D0 GB0002249 D0 GB 0002249D0
Authority
GB
United Kingdom
Prior art keywords
receiving circuit
data receiving
clock recovery
clock
recovery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0002249A
Other versions
GB2359223A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Communication and Control Electronics Ltd
Original Assignee
Communication and Control Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Communication and Control Electronics Ltd filed Critical Communication and Control Electronics Ltd
Priority to GB0002249A priority Critical patent/GB2359223A/en
Publication of GB0002249D0 publication Critical patent/GB0002249D0/en
Publication of GB2359223A publication Critical patent/GB2359223A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
GB0002249A 2000-02-02 2000-02-02 Clock recovery where the clock is synchronised to its own output transitions when there are no input data transitions Withdrawn GB2359223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0002249A GB2359223A (en) 2000-02-02 2000-02-02 Clock recovery where the clock is synchronised to its own output transitions when there are no input data transitions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0002249A GB2359223A (en) 2000-02-02 2000-02-02 Clock recovery where the clock is synchronised to its own output transitions when there are no input data transitions

Publications (2)

Publication Number Publication Date
GB0002249D0 true GB0002249D0 (en) 2000-03-22
GB2359223A GB2359223A (en) 2001-08-15

Family

ID=9884716

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0002249A Withdrawn GB2359223A (en) 2000-02-02 2000-02-02 Clock recovery where the clock is synchronised to its own output transitions when there are no input data transitions

Country Status (1)

Country Link
GB (1) GB2359223A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110492986A (en) * 2019-09-11 2019-11-22 吉林省广播电视研究所(吉林省广播电视局科技信息中心) Single fiber chronometer time predicts synchronous electronic system

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005109733A1 (en) * 2004-05-06 2005-11-17 Igor Anatolievich Abrosimov Clock frequency reduction in communications receiver with coding
DE102008011845A1 (en) * 2007-09-21 2009-04-02 Rohde & Schwarz Gmbh & Co. Kg Method and device for clock recovery

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1571784A (en) * 1978-05-30 1980-07-16 Plessey Co Ltd Clock regenerators
JPS5797751A (en) * 1980-12-10 1982-06-17 Clarion Co Ltd Circuit for adding artificial synchronizing signal
CA2110030C (en) * 1992-11-30 1998-09-15 Fumio Nakano Method and apparatus for clock synchronizing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110492986A (en) * 2019-09-11 2019-11-22 吉林省广播电视研究所(吉林省广播电视局科技信息中心) Single fiber chronometer time predicts synchronous electronic system
CN110492986B (en) * 2019-09-11 2023-06-23 吉林省广播电视研究所(吉林省广播电视局科技信息中心) Single-fiber precise time prediction synchronous electronic system

Also Published As

Publication number Publication date
GB2359223A (en) 2001-08-15

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)