FR3121548A1 - METHOD FOR PREPARING AN ADVANCED SUBSTRATE, IN PARTICULAR FOR PHOTONIC APPLICATIONS - Google Patents
METHOD FOR PREPARING AN ADVANCED SUBSTRATE, IN PARTICULAR FOR PHOTONIC APPLICATIONS Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 230000008021 deposition Effects 0.000 claims abstract description 4
- 238000004544 sputter deposition Methods 0.000 claims abstract description 3
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 7
- 238000012546 transfer Methods 0.000 claims description 6
- 230000003313 weakening effect Effects 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 230000010070 molecular adhesion Effects 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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Abstract
L’invention porte sur un procédé de préparation d’un substrat support (1) comprenant les étapes suivantes : fournir un substrat de base (3) comportant :+ une couche de piégeage de charges (2) disposée sur une face principale (31) du substrat de base (3) ; et+ une couche de compensation de courbure (32) disposée sur une face arrière (33) du substrat de base (3), la face arrière (33) étant opposée à la face principale (31) ;former une couche diélectrique (4) sur la couche de piégeage de charges (2), la formation de la couche diélectrique (4) mettant simultanément en œuvre le dépôt et la pulvérisation ionique de la couche diélectrique. ( Figure 4 )The invention relates to a method for preparing a support substrate (1) comprising the following steps: providing a base substrate (3) comprising:+ a charge trapping layer (2) disposed on a main face (31) the base substrate (3); and+ a curvature compensation layer (32) disposed on a rear face (33) of the base substrate (3), the rear face (33) being opposite the main face (31);forming a dielectric layer (4) on the charge trapping layer (2), the formation of the dielectric layer (4) simultaneously implementing the deposition and the ion sputtering of the dielectric layer. (Figure 4)
Description
DOMAINE DE L’INVENTIONFIELD OF THE INVENTION
La présente invention concerne un procédé de préparation d’un substrat support comprenant une couche de piégeage de charges. Elle concerne également un procédé de report d’une couche mince sur un tel substrat support, pour réaliser un substrat avancé muni de ladite couche de piégeage de charges et éventuellement d’une couche diélectrique épaisse, enterrées sous la couche mince. Ce type de substrats peut trouver une application dans le domaine de la photonique. Ces substrats trouvent également une application notable dans le domaine des dispositifs intégrés radiofréquences, c’est-à-dire des dispositifs électroniques traitant des signaux dont la fréquence est comprise entre environ 3kHz et 300GHz, par exemple dans le domaine des télécommunications (téléphonie, Wi-Fi, Bluetooth…).The present invention relates to a process for preparing a support substrate comprising a charge trapping layer. It also relates to a method for transferring a thin layer onto such a support substrate, to produce an advanced substrate provided with said charge trapping layer and optionally with a thick dielectric layer, buried under the thin layer. This type of substrate can find an application in the field of photonics. These substrates also find a significant application in the field of integrated radio frequency devices, that is to say electronic devices processing signals whose frequency is between about 3 kHz and 300 GHz, for example in the field of telecommunications (telephony, Wi -Fi, Bluetooth…).
ARRIERE PLAN TECHNOLOGIQUE DE L’INVENTIONTECHNOLOGICAL BACKGROUND OF THE INVENTION
Pour se prémunir ou limiter le phénomène de couplage électromagnétique qui peut se produire entre un dispositif électronique ou photonique et le substrat support d’un substrat de silicium sur isolant (SOI) sur lequel ce dispositif est formé, il est connu d'insérer entre la couche diélectrique enterrée et le support du SOI, directement sous la couche diélectrique, une couche de piégeage de charges. Cette couche peut être constituée par exemple d’une couche de 1 à 10 microns de silicium polycristallin. Les joints des grains formant le poly cristal constituent alors des pièges pour les porteurs de charges, ceux-ci pouvant provenir de la couche de piégeage elle-même ou du substrat sous-jacent. De la sorte, on prévient l’apparition d’un plan conducteur sous l’isolant. La fabrication de ce type de substrat SOI bien connu est par exemple décrite dans les documents FR2860341, FR2933233, FR2953640, US2015115480, US7268060, US6544656 ou WO2020008116.To guard against or limit the phenomenon of electromagnetic coupling which can occur between an electronic or photonic device and the support substrate of a silicon-on-insulator (SOI) substrate on which this device is formed, it is known to insert between the buried dielectric layer and the SOI support, directly under the dielectric layer, a charge trapping layer. This layer may consist for example of a layer of 1 to 10 microns of polycrystalline silicon. The boundaries of the grains forming the polycrystal then constitute traps for the charge carriers, these possibly coming from the trapping layer itself or from the underlying substrate. In this way, the appearance of a conductive plane under the insulation is prevented. The manufacture of this type of well-known SOI substrate is for example described in the documents FR2860341, FR2933233, FR2953640, US2015115480, US7268060, US6544656 or WO2020008116.
Pour former un substrat SOI présentant une telle couche de piégeage, on prépare un substrat support en formant une couche de piégeage de charges sur un substrat de base. Puis, on reporte une couche mince sur ce substrat support par l’intermédiaire d’un procédé de transfert de couche, par exemple selon la technologie Smart Cut®. Selon cette technologie, on assemble, typiquement par adhésion moléculaire, un substrat donneur au substrat support, le substrat donneur présentant un plan de fragilisation définissant, avec sa face exposée, la couche mince à reporter. On fracture ensuite le substrat donneur au niveau du plan de fragilisation pour reporter la couche mince sur le substrat support. La couche diélectrique est insérée entre le substrat support et la couche mince, par exemple par oxydation de l’un et/ou de l’autre de ces substrats, avant leur assemblage.To form an SOI substrate having such a trapping layer, a support substrate is prepared by forming a charge trapping layer on a base substrate. Then, a thin layer is transferred onto this support substrate by means of a layer transfer process, for example according to Smart Cut® technology. According to this technology, a donor substrate is assembled, typically by molecular adhesion, to the support substrate, the donor substrate having an embrittlement plane defining, with its exposed face, the thin layer to be transferred. The donor substrate is then fractured at the level of the embrittlement plane to transfer the thin layer onto the support substrate. The dielectric layer is inserted between the support substrate and the thin layer, for example by oxidation of one and/or the other of these substrates, before their assembly.
Dans la technologie Smart Cut®, le plan de fragilisation est obtenu en introduisant des espèces légères (hydrogène et/ou hélium par exemple) dans le substrat donneur, à travers la couche diélectrique lorsque celle-ci est présente, généralement par implantation. L’épaisseur de la couche mince à transférer dicte l’énergie et la dose des espèces à implanter : plus cette épaisseur est importante et plus l’énergie et la dose sont également importantes. Implanter une forte dose à haute énergie n’est pas industriellement favorable aussi. Notamment pour des substrats avec 300 mm de diamètre et plus, il n’existe pas d’équipements pouvant réaliser des implantations ioniques à fort courant à une échelle industrielle. Pour contourner ce problème, il est préférable de former la couche de diélectrique sur le substrat support plutôt que sur le substrat donneur, notamment lorsque cette couche diélectrique est choisie relativement épaisse, par exemple supérieure à 200nm.In Smart Cut® technology, the weakening plane is obtained by introducing light species (hydrogen and/or helium for example) into the donor substrate, through the dielectric layer when the latter is present, generally by implantation. The thickness of the thin layer to be transferred dictates the energy and the dose of the species to be implanted: the greater this thickness, the greater the energy and the dose. Implanting a heavy dose at high energy is not industrially favorable as well. Especially for substrates with a diameter of 300 mm and more, there is no equipment that can perform high-current ion implantation on an industrial scale. To circumvent this problem, it is preferable to form the dielectric layer on the support substrate rather than on the donor substrate, in particular when this dielectric layer is chosen to be relatively thick, for example greater than 200 nm.
Les expériences menées par la demanderesse ont toutefois révélé que la formation d’une couche diélectrique par oxydation d’une couche de piégeage de charge en silicium polycristallin posait de nombreux problèmes. Cette oxydation tend à former un substrat support présentant un état de surface rugueux, qu’il faut donc préparer avant l’étape d’assemblage, par exemple par polissage, ce qui complexifie le procédé. L’interface enterrée entre l’oxyde de silicium et le reste de la couche de poly silicium est également rugueux, ce qui peut poser des problèmes d’inspection optique du substrat SOI lors des étapes de fabrication des dispositifs. De plus, l’étape d’oxydation tend à déformer le substrat support et à faire apparaître une courbure importante (désignée par le terme anglais "bow" dans la technologie de semi-conducteurs). La présence d’une telle courbure rend délicate l’étape suivante d’assemblage.The experiments carried out by the applicant have however revealed that the formation of a dielectric layer by oxidation of a polycrystalline silicon charge trapping layer posed many problems. This oxidation tends to form a support substrate with a rough surface state, which must therefore be prepared before the assembly step, for example by polishing, which complicates the process. The buried interface between the silicon oxide and the rest of the polysilicon layer is also rough, which can pose problems for the optical inspection of the SOI substrate during the device fabrication steps. In addition, the oxidation step tends to deform the support substrate and to cause a significant curvature to appear (designated by the English term “bow” in semiconductor technology). The presence of such a curvature makes the next assembly step tricky.
Par ailleurs, pour réaliser un substrat avancé visant des applications photoniques bénéficiant des avantages d’une couche de piégeage de charges, ledit substrat comporte en outre une couche diélectrique épaisse. L’épaisseur de la couche de diélectrique, autrement dit le BOX, est généralement de l’ordre du micron voire de quelques microns.Furthermore, to produce an advanced substrate aimed at photonic applications benefiting from the advantages of a charge trapping layer, said substrate also comprises a thick dielectric layer. The thickness of the dielectric layer, in other words the BOX, is generally of the order of a micron or even a few microns.
La méthode conventionnelle pour réaliser ce type de structure consiste à déposer une couche très épaisse de silicium polycristallin qui sera polie, avant de l’oxyder thermiquement et de la repolir.The conventional method for producing this type of structure consists of depositing a very thick layer of polycrystalline silicon which will be polished, before thermally oxidizing it and repolishing it.
Les étapes de polissage nécessitent des enlèvements importants, généralement par CMP, pour supprimer la très forte rugosité des différentes couches. Ces étapes de polissage, et d’oxydation thermique de couches très épaisses engendrent des contraintes mécaniques considérables dans les couches et génèrent de ce fait une courbure du substrat très importante (un « bow » pouvant être supérieur à 250 µm). Notons qu’au-delà d’un certain « bow », les substrats ne sont plus compatibles avec la plupart des équipements destinés à les manipuler dans la ligne de production desdits substrats, ainsi que les équipements configurés pour la réalisation des dispositifs finaux sur ce type de substrats. De plus, quand bien même des équipements acceptent de manipuler ce type de substrats avec un important « bow », les dispositifs réalisés sur de tels substrats souffriront d’un désalignement très important (défaut d’alignement de type radial) généré par la courbure importante des substrats.The polishing steps require significant removals, usually by CMP, to remove the very high roughness of the different layers. These polishing and thermal oxidation steps of very thick layers generate considerable mechanical stresses in the layers and therefore generate a very significant curvature of the substrate (a "bow" that can be greater than 250 µm). It should be noted that beyond a certain "bow", the substrates are no longer compatible with most of the equipment intended to handle them in the production line of said substrates, as well as the equipment configured for the production of the final devices on this type of substrates. In addition, even if equipment agrees to handle this type of substrate with a significant "bow", the devices made on such substrates will suffer from very significant misalignment (misalignment of the radial type) generated by the significant curvature substrates.
En outre, une oxydation thermique d’une couche de piégeage de charges induit une très forte rugosité même à l’interface entre la couche diélectrique et la couche de piégeage. Cette interface n’étant pas accessible pour un polissage, elle sera ainsi conservée dans le corps du substrat. Cette forte rugosité peut impacter négativement le bon fonctionnement d’un dispositif, notamment un dispositif photonique, réalisé dans ce type de substrat.In addition, thermal oxidation of a charge trapping layer induces a very high roughness even at the interface between the dielectric layer and the trapping layer. Since this interface is not accessible for polishing, it will thus be kept in the body of the substrate. This high roughness can negatively impact the proper functioning of a device, in particular a photonic device, made in this type of substrate.
On note que la formation de la couche de diélectrique par dépôt sur le substrat support plutôt que par oxydation du support présente des problèmes similaires. En effet, les techniques conventionnelles de dépôt PECVD (acronyme de l’expression anglo-saxonne « Plasma Enhanced Chemical Vapor Deposition » ou dépôt chimique en phase vapeur assisté par plasma) ou LPCVD (acronyme de l’expression anglo-saxonne « Low Pressure Chemical Vapor Deposition » ou dépôt chimique en phase vapeur à pression sous atmosphérique) génèrent des courbures importantes et conduisent généralement à former des couches très rugueuses qu’il faut préparer par polissage avant de pouvoir envisager tout assemblage.It is noted that the formation of the dielectric layer by deposition on the support substrate rather than by oxidation of the support presents similar problems. Indeed, the conventional PECVD deposition techniques (acronym of the Anglo-Saxon expression "Plasma Enhanced Chemical Vapor Deposition" or plasma-assisted chemical vapor deposition) or LPCVD (acronym of the Anglo-Saxon expression "Low Pressure Chemical Vapor Deposition” or sub-atmospheric pressure chemical vapor deposition) generate significant curvatures and generally lead to the formation of very rough layers that must be prepared by polishing before any assembly can be considered.
OBJET DE L’INVENTIONOBJECT OF THE INVENTION
La présente invention vise à pallier tout ou partie des inconvénients précités.The present invention aims to overcome all or part of the aforementioned drawbacks.
BREVE DESCRIPTION DE L’INVENTIONBRIEF DESCRIPTION OF THE INVENTION
En vue de la réalisation de l’un de ces buts, l’objet de l’invention propose un procédé préparation d’un substrat support comprenant les étapes suivantes :With a view to achieving one of these aims, the object of the invention proposes a process for preparing a support substrate comprising the following steps:
-
fournir un substrat de base comportant :
+ une couche de piégeage de charges disposée sur une face principale du substrat de base ; et
+ une couche de compensation de courbure disposée sur une face arrière du substrat de base, la face arrière étant opposée à la face principale ;provide a base substrate comprising:
+ a charge trapping layer placed on a main face of the base substrate; and
+ a curvature compensation layer arranged on a rear face of the base substrate, the rear face being opposite the main face; - former une couche diélectrique sur la couche de piégeage de charges, la formation de la couche diélectrique mettant simultanément en œuvre le dépôt et la pulvérisation ionique de la couche diélectrique.forming a dielectric layer over the charge trapping layer, forming the dielectric layer simultaneously involving deposition and ion sputtering of the dielectric layer.
Selon d’autres caractéristiques avantageuses et non limitatives de l’invention, prises seules ou selon toute combinaison techniquement réalisable :According to other advantageous and non-limiting characteristics of the invention, taken alone or according to any technically feasible combination:
- la couche de compensation est formée par une oxydation thermique du substrat de base, suivie respectivement par une élimination du matériau de la couche de compensation de la face avant, et par la formation de la couche de piégeage de charges et la couche diélectrique, préférentiellement l’oxydation thermique est réalisée à une température comprise entre 800 et 1100 °C.the compensation layer is formed by thermal oxidation of the base substrate, followed respectively by removal of the material of the compensation layer from the front face, and by the formation of the charge trapping layer and the dielectric layer, preferably l Thermal oxidation is carried out at a temperature between 800 and 1100°C.
- la couches de compensation de courbure est en oxyde de silicium ou en nitrure de silicium.the curvature compensation layer is made of silicon oxide or silicon nitride.
- la couche de compensation de courbure présente une épaisseur comprise entre 500 et 1000 nm.the curvature compensation layer has a thickness of between 500 and 1000 nm.
- l’épaisseur de la couche de compensation de courbure est déterminée en fonction d’une valeur de « bow » toléré prédéterminé du substrat support, de l’épaisseur de la couche de piégeage de charges, et de l’épaisseur de la couche diélectrique visées.the thickness of the curvature compensation layer is determined as a function of a predetermined tolerated "bow" value of the support substrate, the thickness of the charge trapping layer, and the thickness of the targeted dielectric layer .
- la couche diélectrique présente une épaisseur supérieure à 200nm, préférentiellement supérieure à 600 nm, et encore plus préférentiellement comprise entre 600 nm et 10 microns.the dielectric layer has a thickness greater than 200 nm, preferably greater than 600 nm, and even more preferably between 600 nm and 10 microns.
Selon un autre aspect, l’objet de l’invention propose un procédé de report d’une couche mince sur un substrat support comprenant les étapes suivantes :
- préparer un substrat support à l’aide d’un procédé de préparation tel que proposé précédemment ;
- assembler, par adhésion moléculaire, un substrat donneur à la couche diélectrique du substrat support, le substrat donneur présentant un plan de fragilisation définissant la couche mince ;
- fracturer le substrat donneur au niveau du plan de fragilisation pour libérer la couche mince et la reporter sur le substrat support.According to another aspect, the object of the invention proposes a process for transferring a thin layer onto a support substrate comprising the following steps:
- preparing a support substrate using a preparation method as proposed above;
- assembling, by molecular adhesion, a donor substrate to the dielectric layer of the support substrate, the donor substrate having a weakening plane defining the thin layer;
- Fracture the donor substrate at the weakening plane to free the thin layer and transfer it onto the support substrate.
Selon une caractéristique avantageuse et non limitative de l’invention, la face libre de la couche diélectrique n’est pas préparée par polissage avant son assemblage au substrat donneur.According to an advantageous and non-limiting characteristic of the invention, the free face of the dielectric layer is not prepared by polishing before its assembly with the donor substrate.
Selon d’autres caractéristiques avantageuses et non limitatives de l’invention, prises seules ou selon toute combinaison techniquement réalisable :According to other advantageous and non-limiting characteristics of the invention, taken alone or according to any technically feasible combination:
- un dispositif photonique est formé sur la couche mince.a photonic device is formed on the thin layer.
- le dispositif photonique forme un commutateur, un guide d’ondes, un déphaseur, un modulateur, un émetteur laser, un amplificateur, un coupleur directionnel, un filtre, et/ou un multiplexeur.the photonic device forms a switch, a waveguide, a phase shifter, a modulator, a laser transmitter, an amplifier, a directional coupler, a filter, and/or a multiplexer.
Selon un autre aspect, l’objet de l’invention propose un substrat support comportant la couche mince élaborée par le procédé de report tel que proposé précédemment et un dispositif photonique intégré dans ladite couche mince.According to another aspect, the object of the invention proposes a support substrate comprising the thin layer produced by the transfer process as proposed above and a photonic device integrated in said thin layer.
D’autres caractéristiques et avantages de l’invention ressortiront de la description détaillée de l’invention qui va suivre en référence aux figures annexées sur lesquels :Other characteristics and advantages of the invention will emerge from the detailed description of the invention which will follow with reference to the appended figures in which:
La
La
Les figures 3A à 3E représentent un mode de réalisation d’un substrat support conforme à l’invention ;FIGS. 3A to 3E represent an embodiment of a support substrate in accordance with the invention;
La
Claims (12)
- fournir un substrat de base (3) comportant :
+ une couche de piégeage de charges (2) disposée sur une face principale (31) du substrat de base (3) ; et
+ une couche de compensation de courbure (32) disposée sur une face arrière (33) du substrat de base (3), la face arrière (33) étant opposée à la face principale (31) ; - former une couche diélectrique (4) sur la couche de piégeage de charges (2), la formation de la couche diélectrique (4) mettant simultanément en œuvre le dépôt et la pulvérisation ionique de la couche diélectrique.
- providing a base substrate (3) comprising:
+ a charge trapping layer (2) arranged on a main face (31) of the base substrate (3); and
+ a curvature compensation layer (32) arranged on a rear face (33) of the base substrate (3), the rear face (33) being opposite the main face (31); - forming a dielectric layer (4) on the charge trapping layer (2), the formation of the dielectric layer (4) simultaneously implementing deposition and ion sputtering of the dielectric layer.
- préparer un substrat support (1) à l’aide d’un procédé conforme à l’une des revendications 1 à 7 ;
- assembler, par adhésion moléculaire, un substrat donneur à la couche diélectrique (4) du substrat support (1), le substrat donneur présentant un plan de fragilisation définissant la couche mince (5) ;
- fracturer le substrat donneur au niveau du plan de fragilisation pour libérer la couche mince (5) et la reporter sur le substrat support (1).Method for transferring a thin layer (5) onto a support substrate (1) comprising the following steps:
- preparing a support substrate (1) using a method according to one of claims 1 to 7;
- assembling, by molecular adhesion, a donor substrate to the dielectric layer (4) of the support substrate (1), the donor substrate having a weakening plane defining the thin layer (5);
- Fracture the donor substrate at the weakening plane to free the thin layer (5) and transfer it to the support substrate (1).
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2103274A FR3121548B1 (en) | 2021-03-30 | 2021-03-30 | METHOD FOR PREPARING AN ADVANCED SUBSTRATE, PARTICULARLY FOR PHOTONIC APPLICATIONS |
| KR1020227041969A KR20230042215A (en) | 2020-07-28 | 2021-06-23 | Process of transferring a thin layer to a carrier substrate with a charge trapping layer |
| PCT/FR2021/051140 WO2022023630A1 (en) | 2020-07-28 | 2021-06-23 | Method for transferring a thin layer onto a support substrate provided with a charge trapping layer |
| US18/007,145 US20230230874A1 (en) | 2020-07-28 | 2021-06-23 | Method for transferring a thin layer onto a support substrate provided with a charge-trapping layer |
| JP2023501665A JP2023535319A (en) | 2020-07-28 | 2021-06-23 | Process of transferring a thin layer to a carrier substrate provided with a charge trapping layer |
| CN202180048518.0A CN115777139A (en) | 2020-07-28 | 2021-06-23 | Method for transferring a thin layer to a carrier substrate provided with a charge-trapping layer |
| EP21740160.3A EP4189734A1 (en) | 2020-07-28 | 2021-06-23 | Method for transferring a thin layer onto a support substrate provided with a charge trapping layer |
| TW110126926A TWI796735B (en) | 2020-07-28 | 2021-07-22 | Process for transferring a thin layer to a carrier substrate provided with a charge-trapping layer |
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| FR2103274A FR3121548B1 (en) | 2021-03-30 | 2021-03-30 | METHOD FOR PREPARING AN ADVANCED SUBSTRATE, PARTICULARLY FOR PHOTONIC APPLICATIONS |
| FR2103274 | 2021-03-30 |
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