FR3118286A1 - STACKING OF THREE OR MORE CHIPS - Google Patents

Abstract

STACK OF AT LEAST THREE ELECTRONIC CHIPS The invention relates to a stack of electronic chips comprising a first chip (10), a second chip (20) and a third chip (30), each of the first, second and third chips comprising a first face (10a, 20a, 30a) and a second face (10b, 20b, 30b) opposite the first face, the first face (10a) of the first chip (10) being glued to the first face (20a) of the second chip (20) by hybrid bonding and the second face (20b) of the second chip (20) being bonded to the first face (30a) of the third chip (30) by hybrid bonding, the second chip comprising a substrate (21) and a plurality of through vias (27) extending through the substrate (21). Abstract Figure: Figure 3

Description

STACKING OF THREE OR MORE CHIPS

The present invention relates to three-dimensional integrated circuits (3D IC) and relates more particularly to a stack of at least three electronic chips making it possible to obtain a high integration density.

STATE OF THE ART

Three-dimensional (3D) integration consists of stacking several electronic chips (also called integrated circuits) and connecting them electrically to each other, for example by a bonding technique. This approach makes it possible in particular to reduce the size of so-called "heterogeneous" systems which are composed of circuits belonging to different generations of the same technology of semiconductor devices or of circuits belonging to different technologies, for example an image sensor comprising a photodiode array and a CMOS image processing circuit comprising logic circuits. 3D integration also makes it possible to increase the density of transistors per unit area without reducing their dimensions, to reduce power consumption and/or to increase the operating speed of a system, by replacing long horizontal interconnects with short vertical interconnects.

A 3D circuit can adopt several 3D stacking architectures depending in particular on the way the chips are stacked, the orientation of the chips and the type of bonding.

Stacking can be carried out according to different approaches: from plate to plate (for "wafer-to-wafer" in English), from chip to plate ("die-to-wafer") or even from chip to chip ("die- to-die”). The plate-to-plate stacking technique is the fastest in terms of the number of chips bonded per hour, because it is a collective bonding at the scale of the silicon wafers. It is also the most accurate for a given bonding speed. On the other hand, unlike the other two techniques, it does not offer the possibility of assembling only the functional chips (known as “Known Good Dies”), selected after a series of tests and the cutting of the plates. The yield after assembly obtained by the plate-to-plate technique is therefore lower than the yield of the chip-to-plate technique or the yield of the chip-to-chip technique as soon as the technological yield for manufacturing the wafers is less than 100%. This last technique is naturally the longest to implement, because the chips are glued together two by two after the plates have been cut.

When the chips (or the plates) are oriented in the same direction, the front face of a chip is glued to the back face of another chip (this assembly mode is called “face-to-back”). Conversely, when the chips (or the plates) are assembled after turning one of them over, the chips are glued front face against front face (“face-to-face”) or rear face against rear face (“back -to-back”).

FIG. 1 illustrates an example of a 3D circuit integrating a first chip 100a and a second chip 100b in a package composed of a substrate 110 and a cover 120. The first chip 100a, called the upper chip, is stacked on the second chip 100b, called lower chip. Each chip comprises, from the rear face BS to the front face FS, a silicon substrate 101, a first functional block 102 (or set of technological levels) called FEOL (“Front End Of Line”) which groups the active components (ex . transistors) of the chip, and a second functional block 103 called BEOL (“Back End Of Line”) which groups together the passive components (e.g. resistors, inductors, capacitors) and the interconnections between the transistors (or blocks of transistors) of the chip. The interconnects of the BEOL block 103 are typically distributed in several levels of metal.

The chips 100a-100b are in this example assembled front face against front face (“face-to-face”) by a hybrid-type direct bonding technique. The bonding surface of each chip is composed of metal (typically copper) interconnect pads 104 and a dielectric material 105 (typically silicon dioxide) that surrounds the interconnect pads 104. The interconnect pads 104 of the first chip 100a are in direct contact with the interconnect pads 104 of the second chip 100b, so as to electrically couple the two chips 100a-100b. The interconnect pads participate in the bonding of the two chips and carry electrical signals from one chip to the other.

Through vias 106 designated by the acronym TSV (from the English "Through Substrate Via" or "Through Silicon Via") also extend through the lower chip 100b, and more particularly the first metal level (M1) from the block BEOL to the rear face BS. These through vias 106 are used to route the electrical signals from the front face FS of the chip 100b to its rear face BS. The substrate 101 of the lower chip 100b is specially thinned to allow the production of these vias.

The signals are then distributed (or redistributed) on the rear face BS of the lower chip 100b, using a redistribution layer 107 called RDL (“redistribution layer”). The role of this RDL layer 107 is to electrically connect each of the TSVs 106 to a contact recovery zone, from which the signals are routed to the exterior of the case.

The article [“Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness”; J. Jourdon et al., 2018 IEEE International Electron Devices Meeting (IEDM), p. 7.3.1-7.1.4, 2018] describes another example of a 3D stack comprising two electronic chips assembled front face to front face (“face-to-face”) by hybrid bonding (Cu/SiO ₂ ). The top chip is a back side illuminated image sensor (BSI) and the bottom chip is an image processing logic circuit made in CMOS technology. The interconnection pads (also called “HBM pads” for “Hybrid Bonding Metal pads” in English) have a repetition pitch of between 1.44 μm and 8.8 μm.

FIG. 2 schematically represents a 3D integrated circuit described in the document [“Pixel/DRAM/logic 3-layer stacked CMOS image sensor technology”; H. Tsugawa et al., 2017 IEEE International Electron Devices Meeting (IEDM), pp. 3.2.1-3.2.4, 2017]. This 3D circuit comprises a stack of three electronic chips (also called "layers"): an image sensor 200a comprising a matrix of pixels, an image processing logic circuit 200b and a memory circuit 200c comprising a matrix of memory cells . The memory circuit 200c is placed between the image sensor 200a and the logic circuit 200b for image processing.

The logic circuit 200b and the memory circuit 200c are first assembled, front face FS against front face FS (“face-to-face”), by direct oxide-oxide bonding. The silicon substrate 201c of the memory circuit 200c is thinned down to 3 μm. Then, TSVs 206c and redistribution tracks 207 are formed simultaneously on the rear face BS of memory circuit 200c. A portion of the TSVs 206c extend through the thinned substrate 201c and the FEOL and BEOL blocks of the memory circuit 200c to the first metal level M1 of the logic circuit 200b in order to connect the memory circuit 200c to the logic circuit 200b. The front face FS of the image sensor 200a is then bonded to the rear face BS of the memory circuit 200c (“face-to-back”) by direct oxide-oxide bonding. The redistribution tracks 207 are buried in a layer of dielectric material 208 and therefore do not participate in the bonding of the chips 200a and 200c. TSVs 206a are formed from the rear face of image sensor 200a after thinning of substrate 201a. A portion of the TSVs 206a extend through the thinned substrate 201a and the FEOL and BEOL blocks of the image sensor 200a to the redistribution tracks 207 of the memory circuit 200c, thereby electrically connecting the image sensor 200a to the memory circuit 200c.

The TSVs 206a and 206c have a diameter of 2.5 μm and a repetition pitch of 6.3 μm. They are located in a zone peripheral to the so-called “active” zone of the stack containing the pixels of the image sensor 200a, the memory cells of the memory circuit 200c and the transistors of the logic circuit 200b. They therefore considerably reduce the chip surface available for these active components. The length of the connections between the pixels, the memory cells and the transistors is important, since the connections include the TSVs of the peripheral zone. As a result, the 3D circuit of Figure 2 has a limited operating speed (despite the integration of the memory chip within the stack) and a large size.

There is a need to provide a stack of electronic chips that can accommodate a greater number of active components with a constant chip surface (or less bulky with a constant number of components) and exhibiting a higher operating speed.

• la première puce comprend une pluralité de premiers plots d’interconnexion débouchant sur la première face de la première puce ;
• la deuxième puce comprend :
  • un substrat ;
  • un ensemble de niveaux d’interconnexion disposé sur une première face du substrat ;
  • une pluralité de deuxièmes plots d’interconnexion reliés à l’ensemble de niveaux d’interconnexion et débouchant sur la première face de la deuxième puce ;
  • une pluralité de troisièmes plots d’interconnexion disposés sur une deuxième face opposée du substrat et débouchant sur la deuxième face de la deuxième puce ;
  • une pluralité de via traversants s’étendant à travers le substrat et reliant une partie au moins des troisièmes plots d’interconnexion à l’ensemble de niveaux d’interconnexion ;
• la troisième puce comprend une pluralité de quatrièmes plots d’interconnexion débouchant sur la première face de la troisième puce ;

et dans lequel une partie au moins des premiers plots d’interconnexion sont en contact avec une partie au moins des deuxièmes plots d’interconnexion et une partie au moins des troisièmes plots d’interconnexion sont en contact avec une partie au moins des quatrièmes plots d’interconnexion.According to one aspect of the invention, there is a tendency to satisfy this need by providing a stack of electronic chips comprising a first chip, a second chip and a third chip, each of the first, second and third chips comprising a first face and a second face opposite the first face, the first face of the first chip being bonded to the first face of the second chip and the second face of the second chip being bonded to the first face of the third chip, stack in which:

• the first chip comprises a plurality of first interconnect pads emerging on the first face of the first chip;
• the second chip includes:
  • a substrate;
  • a set of interconnection levels arranged on a first face of the substrate;
  • a plurality of second interconnect pads connected to the set of interconnect levels and leading to the first face of the second chip;
  • a plurality of third interconnection pads arranged on a second opposite face of the substrate and emerging on the second face of the second chip;
  • a plurality of through vias extending through the substrate and connecting at least a portion of the third interconnect pads to the set of interconnect levels;
• the third chip comprises a plurality of fourth interconnect pads emerging on the first face of the third chip;

and wherein at least a portion of the first interconnect pads are in contact with at least a portion of the second interconnect pads and at least a portion of the third interconnect pads are in contact with at least a portion of the fourth interconnect pads d interconnection.

Thus, the stack according to the first aspect of the invention has two hybrid bonding interfaces, one between the first faces of the first and second chips, the other between the second face of the second chip and the first face of the third chip. Such a configuration allows the first chip and/or the third chip to accommodate more active components (at a constant chip area) or to reduce the area of the chip (at a constant number of components). Indeed, the through-vias are limited to an area located between the third interconnect pads and the set of interconnect levels of the second chip and therefore do not occupy space in the first and third chips.

Furthermore, the length of the connections between the active components is reduced because the connections are made essentially vertically, and no longer offset towards a peripheral zone of the stack as in the 3D circuit of the prior art. The stack of electronic chips then benefits from an increased operating speed and/or reduced consumption.

In a preferred embodiment of the stack, the first face of the first chip, the first face of the second chip and the first face of the third chip are front faces and the second face of the first chip, the second face of the second chip and the second face of the third chip are rear faces.

Preferably, the first chip and/or the third chip also comprises active components located directly above at least part of the through-vias.

Advantageously, at least part of the through vias have a first repetition pitch comprised between 0.3 μm and 200 μm, preferably between 0.4 μm and 4 μm, in a first direction and a second repetition pitch comprised between 0, 3 μm and 200 μm, preferably between 0.4 μm and 4 μm, in a second direction perpendicular to the first direction. The first repetition step may be equal to the second repetition step.

• les via traversants présentent une première dimension comprise entre 0,1 µm et 100 µm, de préférence entre 0,2 µm et 2 µm, dans la première direction et une deuxième dimension comprise entre 0,1 µm et 100 µm, de préférence entre 0,2 µm et 2 µm, dans la deuxième direction ;
• le substrat présente une épaisseur inférieure ou égale à 10 µm, de préférence comprise entre 3 µm et 10 µm ;
• le substrat présente une variation totale d’épaisseur (TTV) inférieure à 2 µm, de préférence inférieure à 0,5 µm, par exemple comprise entre 0,2 µm et 0,4 µm ;
• le substrat est en silicium ; et
• la première puce est un capteur d’images, la deuxième puce est un circuit logique de traitement d’images et la troisième puce est un circuit mémoire.

The stack according to the first aspect of the invention may also have one or more of the characteristics below, considered individually or in all technically possible combinations:

• the through vias have a first dimension comprised between 0.1 μm and 100 μm, preferably between 0.2 μm and 2 μm, in the first direction and a second dimension comprised between 0.1 μm and 100 μm, preferably between 0 .2 μm and 2 μm, in the second direction;
• the substrate has a thickness less than or equal to 10 μm, preferably between 3 μm and 10 μm;
• the substrate has a total thickness variation (TTV) of less than 2 μm, preferably less than 0.5 μm, for example between 0.2 μm and 0.4 μm;
• the substrate is made of silicon; And
• the first chip is an image sensor, the second chip is an image processing logic circuit and the third chip is a memory circuit.

• fournir une première puce et une deuxième puce, la première puce comprenant une pluralité de premiers plots d’interconnexion débouchant sur une première face de la première puce et la deuxième puce comprenant :
  • un substrat ;
  • un ensemble de niveaux d’interconnexion disposé sur une première face du substrat ; et
  • une pluralité de deuxièmes plots d’interconnexion reliés à l’ensemble de niveaux d’interconnexion et débouchant sur une première face de la deuxième puce ;
• coller la première face de la première puce avec la première face de la deuxième puce, en disposant une partie au moins des premiers plots d’interconnexion en contact avec une partie au moins des deuxièmes plots d’interconnexion ;
• former une pluralité de via traversants s’étendant à travers le substrat jusqu’à l’ensemble de niveaux d’interconnexion ;
• former, sur une deuxième face opposée du substrat, une pluralité de troisièmes plots d’interconnexion de sorte qu’une partie au moins des troisièmes plots d’interconnexion soient reliés à l’ensemble de niveaux d’interconnexion par les via traversants et que les troisièmes plots d’interconnexion débouchent sur une deuxième face de la deuxième puce ;
• fournir une troisième puce comprenant une pluralité de quatrièmes plots d’interconnexion débouchant sur une première face de la troisième puce ; et
• coller la deuxième face de la deuxième puce avec la première face de la troisième puce, en disposant une partie au moins des troisièmes plots d’interconnexion en contact avec une partie au moins des quatrièmes plots d’interconnexion.

A second aspect of the invention relates to a method for manufacturing a stack of electronic chips, comprising the following steps:

• providing a first chip and a second chip, the first chip comprising a plurality of first interconnect pads opening onto a first face of the first chip and the second chip comprising:
  • a substrate;
  • a set of interconnection levels arranged on a first face of the substrate; And
  • a plurality of second interconnect pads connected to the set of interconnect levels and leading to a first face of the second chip;
• bonding the first face of the first chip with the first face of the second chip, by arranging at least part of the first interconnection pads in contact with at least part of the second interconnection pads;
• forming a plurality of through-vias extending through the substrate to the set of interconnect levels;
• forming, on a second opposite face of the substrate, a plurality of third interconnection pads so that at least part of the third interconnection pads are connected to the set of interconnection levels by the through-vias and that the third interconnect pads open onto a second face of the second chip;
• providing a third chip comprising a plurality of fourth interconnect pads opening onto a first face of the third chip; And
• bonding the second face of the second chip with the first face of the third chip, by arranging at least part of the third interconnection pads in contact with at least part of the fourth interconnection pads.

In a preferred mode of implementation, the method further comprises a step of thinning the substrate before the step of forming the through vias. The step of thinning the substrate is advantageously carried out after the step of bonding the first face of the first chip with the first face of the second chip.

The substrate thinning step may comprise a first coarse grinding operation and a second fine grinding operation. The step of thinning the substrate can also be carried out by dry etching or wet etching.

BRIEF DESCRIPTION OF FIGURES

Other characteristics and advantages of the invention will emerge clearly from the description which is given below, by way of indication and in no way limiting, with reference to the following figures.

represents a first example of a stack of electronic chips according to the prior art.

represents a second example of a stack of electronic chips according to the prior art.

represents a preferred embodiment of a stack of electronic chips according to a first aspect of the invention.

to [Fig. 4F] represents steps of a method of manufacturing a stack of electronic chips according to a second aspect of the invention.

For greater clarity, identical or similar elements are identified by identical reference signs in all the figures.

DETAILED DESCRIPTION

FIG. 3 is a partial and schematic sectional view of a stack of electronic chips according to a preferred embodiment of the invention.

The stack comprises at least three electronic chips, a first chip 10 called upper chip, a second chip 20 called intermediate chip and a third chip 30 called lower chip. Each of the first, second and third chips 10, 20, 30 comprises a substrate 11, 21, 31, active components 12, 22, 32 formed in the substrate and one or more metal interconnect levels 13, 23, 33 connecting the active components. Substrates 11, 21 and 31 comprise a layer of semiconductor material, for example silicon. The active components 12, 22, 32 of the same chip belong to a first functional block (or set of technological levels) called "Front End Of Line" or FEOL, while the metal interconnection levels 13, 23, 33 d he same chip belong to a second functional block called “Back End Of Line” or BEOL. Depending on the type of electronic chip (or circuit), the active components 12, 22, 32 can be transistors, photodiodes, memory cells, etc.

By way of example, the first chip 10 is an image sensor comprising a matrix of pixels, each pixel comprising one or more photodiodes 12 formed in the substrate 11, the second chip 20 is an image processing logic circuit comprising a plurality of transistors 22 and the third chip 30 is a memory circuit comprising an array of memory cells 32, for example dynamic random access memory (DRAM) cells.

Each of the first, second and third chips 10, 20, 30 has a first face 10a, 20a, 30a and a second face 10b, 20b, 30b opposite the first face. As illustrated in FIG. 3, the first face 10a of the first chip 10 is glued to the first face 20a of the second chip 20 and the second face 20b of the second chip 20 is glued to the first face 30a of the third chip 30 The chips 10, 20, 30 are assembled together by a direct bonding technique (ie without introducing any intermediate compound − such as an adhesive, a wax or a low melting point alloy − at the level of the bonding interface) of the hybrid metal-dielectric type.

In this preferred embodiment, the first face 10a, 20a, 30a of each of the chips is a front face and the second face 10b, 20b, 30b of each of the chips is a rear face. The front face of a chip designates the face under which is located the BEOL block comprising the interconnection levels (then comes the FEOL block and finally the substrate). The front and rear faces of a chip can also be defined with respect to the two opposite faces of the substrate from which the chip is made, the front face of the chip corresponding to the front face of the substrate on which the active components are successively formed. (FEOL) and the metal interconnect levels (BEOL), and the rear face of the chip corresponding to the rear face of the substrate. Two faces are said here to be “corresponding” when they are merged or facing each other.

Thus, the first and second chips 10-20 are glued here according to the front face-to-front face (“face-to-face”, or F2F) assembly mode and the second and third chips 20-30 are glued according to the mode face-to-back, or F2B assembly.

For bonding purposes, the first chip 10 includes a plurality of first interconnect pads 14 opening onto its first face 10a and the second chip 20 includes a plurality of second interconnect pads 24a opening onto its first face 20a. At least part of the first interconnection pads 14 of the first chip 10 are in (direct) contact with at least part of the second interconnection pads 24a of the second chip 20 in order to electrically couple the first and second chips 10, 20.

The first interconnection pads 14 are distinct and contained in a first dielectric layer 15, formed by a first electrically insulating material. The first interconnection pads 14 and the first dielectric layer 15 form, at the level of the first face 10a of the first chip 10, a first so-called mixed bonding surface (because it is composed of metal and of dielectric material). Likewise, the second interconnection pads 24a are distinct and contained in a second dielectric layer 25a, made up of the first electrically insulating material. The second interconnection pads 24a and the second dielectric layer 25a form at the level of the first face 20a of the second chip 10 a second mixed bonding surface.

The first interconnection pads 14 and the second interconnection pads 24a are made of the same metal, for example copper (Cu), aluminum (Al), tungsten (W), titanium (Ti) or titanium nitride (TiN). The first electrically insulating material, common to the first and second dielectric layers 15, 25a, is for example silicon dioxide (SiO ₂ ). It coats the first interconnect pads 14 and the second interconnect pads 24a. The metal and the first electrically insulating material both participate in the bonding of the first and second chips 10, 20.

The first chip 10 further comprises a plurality of first vias 16 connecting at least part of the first interconnection pads 14 to the BEOL block of the first chip 10 (in other words to the set of interconnection levels), and preferentially to the last metal level Mx of the block BEOL (i.e. the metal level farthest from the substrate 11). Similarly, the second chip 20 further comprises a plurality of second vias 26 connecting at least part of the second interconnection pads 24a to the BEOL block of the second chip 20, and preferably to the last metal level My of the BEOL block.

Like the first and second interconnection pads 14, 24, the first and second vias 16, 26 are coated with an electrically insulating material (identical to or different from the first electrically insulating material). The first and second vias 16, 26 are preferably formed from the same metal as the first and second interconnect pads 14, 24.

The second chip 20 further comprises a plurality of third interconnect pads 24b opening onto its second face 20b and the third chip 30 comprises a plurality of fourth interconnect pads 34 opening onto its first face 30a. At least part of the third interconnection pads 24b of the second chip 20 are in (direct) contact with at least part of the fourth interconnection pads 34 of the third chip 30 in order to electrically couple the second and third chips 20, 30.

The third interconnection pads 24b are distinct and contained in a third dielectric layer 25b, formed by a second electrically insulating material. The third interconnection pads 24b and the third dielectric layer 25b form, at the level of the second face 20b of the second chip 20, a third mixed bonding surface. Likewise, the fourth interconnection pads 34 are distinct and contained in a fourth dielectric layer 35, made up of the second electrically insulating material. The fourth interconnection pads 34 and the fourth dielectric layer 35 form at the level of the first face 30a of the third chip 30 a fourth mixed bonding surface.

The third interconnection pads 24b and the fourth interconnection pads 34 are made of the same metal, chosen for example from copper (Cu), aluminum (Al), tungsten (W), titanium (Ti ) and titanium nitride (TiN). The second electrically insulating material may be identical to the first electrically insulating material (eg SiO ₂ ). It coats the third interconnect pads 24b and the fourth interconnect pads 34.

The third chip 30 further comprises a plurality of third vias 36 connecting at least part of the fourth interconnection pads 34 to the BEOL block of the third chip 30, and preferably to the last metal level Mz of the BEOL block. The third vias 36 are preferably formed from the same metal as the third and fourth interconnection pads 24b, 34. They are also coated with an electrically insulating material (identical to or different from the second electrically insulating material).

The interconnection pads, also called hybrid bonding pads (or HBM pads, for "Hybrid Bonding Metal" in English), the dielectric layer that surrounds them and any vias to which the interconnection pads are connected, called bonding vias (HBV, for “Hybrid Bonding Via”), form a hybrid bonding level (HBL, for “Hybrid Bonding Level”) arranged on the BEOL block of each of the first, second and third chips 10, 20, 30.

The bonding surfaces are substantially planar, their topology generally not exceeding 15 nm. There is then no space between the chips after their bonding, unlike other assembly technologies (typically by microbeads or micro-pillars), which have a large topology (of the order of a few µm) and require the introduction of a polymer between the chips.

One or more interconnect pads of the first chip, the second chip and/or the third chip may not be in contact with another interconnect pad (belonging to an adjacent chip). These interconnection pads, called "dummies", are essentially intended to increase the metal density of the bonding surface, in order to facilitate obtaining a flat surface by chemical-mechanical polishing (CMP). They have no electrical function but participate indirectly in the bonding of chips.

Finally, the second chip 20 comprises a plurality of through vias 27 connecting all or part of the third interconnection pads 24b to the BEOL block of the second chip 20, preferably to the first metal level M1 of the BEOL block. Unlike the first, second and third vias 16, 26, 36, the through vias 27 extend through a substrate, that of the second chip 20. They can therefore be qualified as TSVs. The TSVs 27 extend from the third interconnect pads 24b to the BEOL block, preferably in a direction perpendicular to the first and second faces 20a-20b of the second chip 20.

Thanks to the TSVs 27 and to the additional hybrid bonding level formed on the second face of the substrate 21, an essentially vertical electrical connection can be made between the three chips of the stack. The stack is notably devoid of redistribution layers (distinct from the metal levels of the BEOL) extending parallel to the first and second faces of the chips. This configuration reduces the length of the interconnections between the active components of the different chips. The stack thus forms a 3D circuit benefiting from high operating speed and/or low power consumption.

Furthermore, the TSVs 27 being located only in the lower part of the second chip 20, between the second face 20b of the substrate 21 and the BEOL block, they in no way limit the space available for the active components of the first chip and/or of the third chip (unlike the TSVs 206a of Figure 2, which reduce the area available for the photodiodes). Active components of the first chip 10 and/or of the third chip 30 are advantageously placed directly above the TSVs 27 (respectively above and/or below according to the orientation of FIG. 3).

Preferably, each TSV 27 connects a single interconnect pad 24b to the BEOL block of the second chip 20. A part of the third interconnect pads 24b may not be connected to TSVs, as shown in Figure 3.

In a plane parallel to the first and second faces 20a-20b of the second chip 20, at least part of the TSVs 27 are advantageously arranged in rows and columns, in the form of a matrix. In other words, these TSVs are regularly spaced from each other, both in the direction of the rows and in the direction of the columns. Other TSVs 27, such as the one on the left in Figure 3, can on the contrary be isolated.

The TSVs 27 organized in a matrix thus have a first repetition pitch P _X in a first direction X and a second repetition pitch P _Y in a second direction Y perpendicular to the first direction X.

Advantageously, the first repetition pitch P _X is between 0.3 μm and 200 μm, preferably between 0.4 μm and 4 μm, and the second repetition pitch P _Y is between 0.3 μm and 200 μm , preferably between 0.4 μm and 4 μm. Thus, a high density of interconnections can be achieved and it becomes possible to address the active components (typically the photodiodes of the image sensor) individually. The repetition pitches P _X and P _Y are preferably equal.

In a variant embodiment, the TSVs 27 are not arranged in a matrix and have no repetition pitch.

The section of the TSVs 27 (in a plane parallel to the first and second faces 20a-20b of the second chip 20) can be of any shape, for example rectangular, round, ellipsoidal or octagonal.

The TSVs 27 have dimensions in the X and Y directions, denoted respectively by D _X and D _Y , which can be between 0.1 μm and 100 μm, preferably between 0.2 μm and 2 μm. Preferably, the dimension D _X in X of the TSVs 27 is equal to the first repetition pitch P _x divided by 2 (D _X = P _x /2) and the dimension D _Y in Y is equal to the second repetition pitch P _Y divided by 2 (D _Y = P _Y /2). The TSVs 27 are, for example, straight circular cylinders of diameter D _X =P _X /2.

The first interconnection pads 14 advantageously have, in each of the X and Y directions, a repetition pitch identical to that of the second interconnection pads 24a. The repetition pitches in X and in Y of the first and second interconnection pads 14, 24a can be between 500 nm and 10 μm. Similarly, the third interconnection pads 24b advantageously have, in each of the X and Y directions, a repetition pitch identical to that of the fourth interconnection pads 34, and preferably to that of the TSVs 27. The repetition pitches in X and Y of the third and fourth interconnection pads 24b, 34 can be between 0.3 μm and 200 μm, preferably between 0.4 μm and 4 μm.

FIGS. 4A to 4F schematically represent steps S1 to S6 of a method for manufacturing a stack of electronic chips, such as that illustrated by FIG. 3.

Step S1 represented by FIG. 4A is a step for preparing the first and second chips 10-20, prior to bonding them. As previously indicated, each chip 10, 20 comprises a substrate 11, 21, one or more metal interconnect levels 13, 23 disposed on the substrate (only one level is shown for clarity) and a hybrid bonding level HBL arranged on the metallic interconnection level(s) 13, 23. The hybrid bonding level HBL of the first chip 10 comprises the first interconnection pads 14 (HBM) and the first vias 16 (HBV ), while the hybrid bonding level HBL of the second chip 20 comprises the second interconnection pads 24a and the second vias 26.

The interconnection pads 14, 24a and the vias 16, 26 can be formed substantially in the same way as the metallic interconnection levels 13, 23, for example by a process of the simple damascene or dual damascene type. This type of process comprises in particular a step of depositing one or more dielectric layers (for example depositing dielectric material (SiO _x or SiCN or other)/SiN/TEOS, photolithography and etching steps to form cavities in the ( or the) dielectric layer(s), preferably an annealing step for drying the dielectric material (for example TEOS) optionally followed by a step of depositing a barrier layer and/or a layer of metallic seeding at the bottom and against the side walls of the cavities, the filling of the cavities with a metal such as copper (for example by electrochemical deposition) and a step of mechanical-chemical polishing (CMP) of the layer of metal until obtaining a substantially planar mixed bonding surface.

At step S2 of FIG. 4B, the first and second chips 10, 20 are glued together, first face against first face (here bonding interface F2F), by putting the first interconnection pads 14 in contact with the second pads interconnection 24a. The bonding surfaces can be brought into contact at ambient temperature and atmospheric pressure. It can also be carried out under vacuum (at room temperature or not). It is preferably followed by an annealing operation, for example at 400° C. for 2 hours.

The bonding of the first and second chips 10-20, as well as the bonding of the third chip 30 described later, are preferably carried out on the scale of the plates (“wafers”), in other words according to the “plate to plate” approach. (“wafer-to-wafer”). Thus, a first plate comprising a plurality of first chips 10 is glued to a second plate comprising a plurality of second chips 20.

Alternatively, one or more chip bondings can be made using the die-to-wafer approach.

The first interconnect pads 14 may not be perfectly aligned with the second interconnect pads 24a, as shown in Figure 4B. The misalignment between the interconnection pads obtained in plate-to-plate bonding is typically less than 100 nm (3σ value).

The substrate 11 of the first chip 10 (eg image sensor) can be thinned, by grinding or etching, after the bonding of the first and second chips 10-20.

FIG. 4C represents a step S3 for thinning the substrate 21 of the second chip 20, according to a preferred mode of implementation of the manufacturing method.

The thinning of the substrate 21 is accomplished before the formation of the TSVs 27 of the second chip 20, and preferably after the bonding of the first and second chips 10, 20 (step S2; Fig.4B). This avoids the use of a temporary substrate called a handle to thin the substrate 21 and stick the second chip 20 to the first chip 10.

The substrate 21 of the second chip 20 initially has a thickness which can be between 500 μm and 800 μm. It is advantageously thinned to obtain a thickness less than or equal to 10 μm, and preferably between 3 μm and 10 μm. The thinning of the substrate 21 greatly facilitates the manufacture of TSVs of small dimensions in X and in Y (typically between 0.2 μm and 2 μm), due to a smaller form factor, but also the alignment of the TSVs 27 on the metal level of the BEOL block.

This thinning also makes it possible to use a bulk silicon substrate as the substrate of the second chip 20, rather than a more expensive silicon-on-insulator (SOI) substrate. Indeed, in the processes of the prior art, SOI substrates are generally used because they are easier to thin compared to a solid substrate (the buried oxide layer of the SOI substrate serves as a stop layer at a step of engraving).

The substrate 21 can be thinned by grinding. Preferably, the step of thinning the substrate 21 comprises two grinding operations: a first coarse grinding operation, then a second fine grinding operation. For example, coarse grinding is accomplished using a first diamond wheel comprising grains of synthetic diamond approximately 40 µm in size (mesh size #320), while fine grinding is accomplished using a second diamond wheel comprising grains of synthetic diamond approximately 2 to 4 µm in size (mesh size #8000). The grains of the first diamond wheel are coated with a first polymer material (binder) and the grains of the second diamond wheel are coated with a second polymer material, different from the first polymer material Coarse grinding decreases the thickness of the substrate 21 to an intermediate value between 100 μm and 300 μm, for example 200 μm, then the fine grinding reduces the thickness of the substrate 21 to a value less than or equal to approximately 10 μm.

An automatic adjustment of the total thickness variation (or TTV, for "Total Thickness Variation" in English) can be carried out during the first grinding operation and/or the second grinding operation. The automatic adjustment of the TTV improves the precision on the final thickness of the substrate 21. At the end of the thinning step S3, the total variation in thickness of the substrate 21 is advantageously less than 2 μm, preferably less than 0.5 μm, for example between 0.2 μm and 0.4 μm.

The second grinding operation (fine grinding) can also be followed by a chemical-mechanical polishing (CMP) operation, in order to eliminate the hardened zone generated by the diamond wheel and obtain a flat surface. The thickness of the substrate 21 is for example reduced by 400 nm by CMP.

The substrate 21 can also be thinned by a dry or wet etching operation, alone or in combination with one or more grinding operations. For this purpose, the substrate may have different doping levels in order to control the etching more precisely.

With reference to FIG. 4D, the method then comprises a step S4 of forming the TSVs 27 through the substrate 21, up to a metal interconnection level 23 of the second chip 20 (typically the first metal level M1).

• dépôt d’un masque dur 28 (par exemple en TEOS et d’épaisseur comprise entre 500 nm et 2,5 µm) sur la deuxième face 20b du substrat 21 ;
• photolithographie et gravure du substrat 21 à travers le masque dur 28 de façon à former des cavités, puis gravure partielle au fond des cavités de la couche diélectrique intermédiaire 29 séparant le niveau de métal du substrat 21 ;
• formation d’une couche électriquement isolante (par exemple en TEOS) contre les parois latérales des cavités ;
• gravure de la couche diélectrique intermédiaire 29 restante jusqu’à déboucher sur le niveau d’interconnexion 23 ;
• dépôt au fond et contre les parois latérales des cavités d’une couche barrière (ex. Ti/TiN), de préférence par MOCVD (« Metal Organic Chemical Vapor Deposition » en anglais), et/ou d’une première couche de germination métallique (ex. Cu), de préférence par dépôt électrochimique, et d’une deuxième couche de germination EG-seed (par électro-greffage) pour avoir un remplissage total de métal (c.-à-d. sans vide) ;
• remplissage des cavités par un métal tel que le cuivre (Cu), l’aluminium (Al), le tungstène (W) ou le titane (Ti), par exemple par dépôt électrochimique (Cu, W) ou dépôt et gravure (Al, Ti) ; et
• polissage mécano-chimique (CMP) pour éliminer l’excès de métal ainsi que la couche barrière et/ou la couche de germination à la surface du masque dur 28.

The step S4 for forming the TSVs 27 may in particular comprise the following operations:

• deposition of a hard mask 28 (for example made of TEOS and with a thickness of between 500 nm and 2.5 μm) on the second face 20b of the substrate 21;
• photolithography and etching of substrate 21 through hard mask 28 so as to form cavities, then partial etching at the bottom of the cavities of intermediate dielectric layer 29 separating the metal level from substrate 21;
• formation of an electrically insulating layer (for example of TEOS) against the side walls of the cavities;
• etching of the remaining intermediate dielectric layer 29 until it leads to the interconnection level 23;
• deposition at the bottom and against the side walls of the cavities of a barrier layer (e.g. Ti/TiN), preferably by MOCVD (“Metal Organic Chemical Vapor Deposition”), and/or of a first metallic seed layer (eg Cu), preferably by electrochemical deposition, and a second EG-seed seed layer (by electro-grafting) to have a total filling of metal (ie without voids);
• filling of the cavities with a metal such as copper (Cu), aluminum (Al), tungsten (W) or titanium (Ti), for example by electrochemical deposition (Cu, W) or deposition and etching (Al, Ti); And
• chemical-mechanical polishing (CMP) to eliminate the excess metal as well as the barrier layer and/or the seed layer on the surface of the hard mask 28.

In step S5 of FIG. 4E, the second level of hybrid bonding of the second chip 20 is formed on the second face 21b of the substrate 21, in contact with the TSVs 27 formed in the previous step S4. This second level of hybrid bonding includes the third interconnection pads 24b.

The third interconnect pads 24b are formed so as to be connected to the metal interconnect level 23 by the TSVs 27, and preferably according to a method identical to that used to form the second interconnect pads 24b of the second chip 20 or the first interconnect pads 14 of the first chip 10 (damascene type process described in relation to FIG. 4A).

Finally, after having prepared the hybrid bonding level HBL of the third chip 30 (comprising the fourth interconnection pads 34 and the third vias 36), preferably in the manner described in relation with FIG. 4A, the first face 30a of the third chip 30 is glued to the second face 20b of the second chip 20 (on which the third interconnection pads 24b open) in step S6 of FIG. 4F. The third interconnection pads 24b are arranged in contact with the fourth interconnection pads 34. The contacting is preferably carried out at ambient temperature and at atmospheric pressure. It is preferably followed by an annealing operation, for example at 400° C. for 2 hours.

Many variations and modifications of the stack of electronic chips and of its method of manufacture will occur to those skilled in the art. The stack may in particular comprise more than three electronic chips. For example, the steps of thinning (S3), of forming the TSVs (S4) and of forming a second level of hybrid bonding (S5) can be reproduced with the substrate of the first chip 10 or the substrate of the third chip 30 in order to stick the first side of a fourth chip there. Furthermore, the stack can be made from chip to plate (“die-to-wafer”) or from chip to chip (“die-to-die”), rather than plate to plate.

Finally, assembly modes other than those described above are possible for bonding the first, second and third chips. The first hybrid bonding may be carried out between the rear face of the first chip (eg image sensor) and the front face of the second chip (eg logic circuit) (F2B assembly mode). The second hybrid bonding may be carried out between the rear face of the second chip and the rear face of the third chip (B2B assembly mode). Other TSVs are then formed in the substrate of the first chip and/or that of the third chip to connect the interconnection pads of the hybrid bonding level to the functional block BEOL.

Claims (15)

Stack of electronic chips comprising a first chip (10), a second chip (20) and a third chip (30), each of the first, second and third chips comprising a first face (10a, 20a, 30a) and a second face ( 10b, 20b, 30b) opposite the first face, the first face (10a) of the first chip (10) being glued to the first face (20a) of the second chip (20) and the second face (20b) of the second chip (20) being bonded to the first face (30a) of the third chip (30), stack in which:

• the first chip (10) comprises a plurality of first interconnect pads (14) emerging on the first face (10a) of the first chip;
• the second chip (20) comprises:
  • a substrate (21);
  • a set (BEOL) of interconnection levels (23) arranged on a first face of the substrate (21);
  • a plurality of second interconnection pads (24a) connected to the set (BEOL) of interconnection levels (23) and emerging on the first face (20a) of the second chip (20);
  • a plurality of third interconnection pads (24b) arranged on a second opposite face of the substrate (21) and emerging on the second face (20b) of the second chip (20); And
  • a plurality of through-vias (27), extending through the substrate (21) and connecting at least part of the third interconnection pads (24b) to the set (BEOL) of interconnection levels (23);
• the third chip (30) comprises a plurality of fourth interconnect pads (34) opening onto the first face (30a) of the third chip;

and wherein at least a portion of the first interconnect pads (14) are in contact with at least a portion of the second interconnect pads (24a) and at least a portion of the third interconnect pads (24b) are in contact with at least part of the fourth interconnect pads (34). Stack according to Claim 1, in which the first chip (10) and/or the third chip (30) further comprises active components (12, 22) located directly above at least part of the through-vias (27 ). Stack according to one of Claims 1 and 2, in which at least part of the through vias (27) have a first repetition pitch (P _X ) of between 0.3 µm and 200 µm, preferably between 0.4 µm and 4 μm, in a first direction (X) and a second repetition pitch (P _Y ) comprised between 0.3 μm and 200 μm, preferably comprised between 0.4 μm and 4 μm, in a second direction (Y) perpendicular to the first direction (X). Stack according to Claim 3, in which the first repetition pitch (P _X ) is equal to the second repetition pitch (P _Y ). Stack according to one of Claims 3 and 4, in which the through-vias (27) have a first dimension (D _X ) of between 0.1 µm and 100 µm, preferably between 0.2 µm and 2 µm, in the first direction (X) and a second dimension (D _Y ) comprised between 0.1 μm and 100 μm, preferably between 0.2 μm and 2 μm, in the second direction (Y). Stack according to any one of Claims 1 to 5, in which the substrate (21) has a thickness less than or equal to 10 µm, preferably between 3 µm and 10 µm. Stack according to any one of Claims 1 to 6, in which the substrate (21) has a total thickness variation (TTV) of less than 2 µm, preferably less than 0.5 µm. Stack according to any one of Claims 1 to 7, in which the substrate (21) is made of silicon. Stack according to any one of Claims 1 to 8, in which the first chip (10) is an image sensor, the second chip (20) is an image processing logic circuit and the third chip (30) is a memory circuit. Stack according to any one of Claims 1 to 9, in which the first face (10a) of the first chip (10), the first face (20a) of the second chip (20) and the first face (30a) of the third chip (30) are front faces and wherein the second face (10b) of the first chip (10), the second face (20b) of the second chip (20) and the second face (30b) of the third chip (30) are rear faces. Method for manufacturing a stack of electronic chips, comprising the following steps:

• providing (S1) a first chip (10) and a second chip (20), the first chip (10) comprising a plurality of first interconnect pads (14) opening onto a first face (10a) of the first chip and the second chip (20) comprising:
  • a substrate (21);
  • a set (BEOL) of interconnection levels (23) arranged on a first face of the substrate (21); And
  • a plurality of second interconnection pads (24a) connected to the set (BEOL) of interconnection levels (23) and emerging on a first face (20a) of the second chip (20);
• bonding (S2) the first face (10a) of the first chip (10) with the first face (20a) of the second chip (20), by arranging at least part of the first interconnection pads (14) in contact with at least part of the second interconnect pads (24a);
• forming (S4) a plurality of through-vias (27) extending through the substrate (21) to the set (BEOL) of interconnect levels (23);
• forming (S5), on a second opposite face of the substrate (21), a plurality of third interconnection pads (24b) so that at least part of the third interconnection pads are connected to the assembly (BEOL) of interconnection levels (23) by the through vias (27) and that the third interconnection pads (24b) open onto a second face (20b) of the second chip (20);
• providing a third chip (30) comprising a plurality of fourth interconnect pads (34) opening onto a first face (30a) of the third chip; And
• bonding (S6) the second face (20b) of the second chip (20) with the first face (30a) of the third chip (30), by arranging at least part of the third interconnection pads (24b) in contact with at least part of the fourth interconnect pads (34).

Method according to claim 11, further comprising a step (S3) of thinning the substrate (21) before the step (S4) of forming the through vias (27). Method according to claim 12, in which the step (S3) of thinning the substrate (21) is performed after the step (S2) of bonding the first face (10a) of the first chip (10) with the first face (20a) of the second chip (20). Method according to one of Claims 12 and 13, in which the step (S3) of thinning the substrate (21) comprises a first operation of coarse grinding and a second operation of fine grinding. Method according to one of Claims 12 and 13, in which the step (S3) of thinning the substrate (21) is carried out by dry etching or wet etching.