FR3115901B1 - System-on-chip binary tree summation of floating-point values - Google Patents

System-on-chip binary tree summation of floating-point values Download PDF

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Publication number
FR3115901B1
FR3115901B1 FR2011342A FR2011342A FR3115901B1 FR 3115901 B1 FR3115901 B1 FR 3115901B1 FR 2011342 A FR2011342 A FR 2011342A FR 2011342 A FR2011342 A FR 2011342A FR 3115901 B1 FR3115901 B1 FR 3115901B1
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FR
France
Prior art keywords
carry out
binary tree
floating
point values
summation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2011342A
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French (fr)
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FR3115901A1 (en
Inventor
Philippe Dore
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Priority to FR2011342A priority Critical patent/FR3115901B1/en
Priority to PCT/EP2021/078419 priority patent/WO2022096246A1/en
Publication of FR3115901A1 publication Critical patent/FR3115901A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4498—Finite state machines

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Devices For Executing Special Programs (AREA)
  • Supply And Distribution Of Alternating Current (AREA)

Abstract

Système sur puce de sommation en arbre binaire de valeurs flottantes intermédiaires, une valeur flottante intermédiaire résultant d'un nombre respectif de valeurs flottantes sommées, comprenant : - un automate (1) à pile configuré pour réaliser des opérations de décalage, de réduction, de vidage et d'acceptation; et - un désambigüiseur (10) configuré pour mettre en œuvre un critère de désambiguïsation permettant de réaliser l'opération de décalage lorsqu'il est faux et de réaliser l'opération de réduction lorsqu'il est vrai, et permettant, lorsque l'automate (1) traite l'information (eof) représentative de la fin de la réception des valeurs flottantes intermédiaires à additionner, de réaliser l'opération de vidage lorsqu'il est faux et de réaliser l'opération de réduction lorsqu'il est vrai. Figure pour l’abrégé : Fig. 1System-on-chip for binary tree summation of intermediate float values, an intermediate float value resulting from a respective number of summed float values, comprising: - a battery-powered automaton (1) configured to carry out shift, reduction, dump and acceptance; and - a disambiguator (10) configured to implement a disambiguation criterion making it possible to carry out the shift operation when it is false and to carry out the reduction operation when it is true, and allowing, when the automaton (1) processes the information (eof) representative of the end of the reception of the intermediate float values to be added, to carry out the emptying operation when it is false and to carry out the reduction operation when it is true. Figure for the abstract: Fig. 1

FR2011342A 2020-11-05 2020-11-05 System-on-chip binary tree summation of floating-point values Active FR3115901B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR2011342A FR3115901B1 (en) 2020-11-05 2020-11-05 System-on-chip binary tree summation of floating-point values
PCT/EP2021/078419 WO2022096246A1 (en) 2020-11-05 2021-10-14 System-on-a-chip for binary tree summation of floating values

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2011342A FR3115901B1 (en) 2020-11-05 2020-11-05 System-on-chip binary tree summation of floating-point values
FR2011342 2020-11-05

Publications (2)

Publication Number Publication Date
FR3115901A1 FR3115901A1 (en) 2022-05-06
FR3115901B1 true FR3115901B1 (en) 2022-11-18

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FR2011342A Active FR3115901B1 (en) 2020-11-05 2020-11-05 System-on-chip binary tree summation of floating-point values

Country Status (2)

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FR (1) FR3115901B1 (en)
WO (1) WO2022096246A1 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3655570A (en) 1968-02-08 1972-04-11 Takeda Chemical Industries Ltd Detergent containing alkali protease
US6125379A (en) * 1998-02-11 2000-09-26 The Research Foundation Of State University Of New York Parallel VLSI shift switch logic devices
WO2017185203A1 (en) * 2016-04-25 2017-11-02 北京中科寒武纪科技有限公司 Device and method for adding up plurality of floating point numbers

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Publication number Publication date
WO2022096246A1 (en) 2022-05-12
FR3115901A1 (en) 2022-05-06

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