WO2017185203A1

WO2017185203A1 - Device and method for adding up plurality of floating point numbers

Info

Publication number: WO2017185203A1
Application number: PCT/CN2016/080126
Authority: WO
Inventors: 郭崎; 周聖元; 李震; 陈云霁; 陈天石
Original assignee: 北京中科寒武纪科技有限公司
Priority date: 2016-04-25
Filing date: 2016-04-25
Publication date: 2017-11-02

Abstract

A device and method for adding up a plurality of floating point numbers. The device comprises a preprocessing module, an addition operation module and a normalizing module. The preprocessing module pre-processes a plurality of floating point numbers such that the exponent bits and the sign bits of the plurality of floating point numbers are aligned. The addition operation module adds up the plurality of pre-processed floating point numbers, so as to obtain an accumulation result and the number of bits to be shifted for the accumulation result. The normalizing module shifts the sign bit, exponent bits and mantissa bits of the accumulation result according to the number of bits to be shifted so as to obtain a normalized accumulation result. The present device and method have the advantages of low operation delay and small precision loss for the result when a plurality of floating point numbers are added up.

Description

Apparatus and method for performing multiple floating point number addition

Technical field

The present invention provides an apparatus and method for performing a plurality of floating point number additions, which can be used for image processors, digital processors, smart devices, and on-chip network data operations.

Background technique

With the advent of the era of big data, the amount of data calculation has also increased significantly, and higher requirements have been placed on the speed of computing. Processors such as images and digital must meet the low-latency, high-accuracy computing requirements. Floating-point addition, as one of the most basic and most commonly used floating-point operations, how to speed up such operations is also particularly important and has led to extensive discussion and research.

The existing accelerometers for adding operands are mainly divided into two types, a serial carry addition tree and a carry save addition tree.

Figure 1 shows the structure of the serial carry addition tree, that is, the structure of the binary tree is used, the operands to be operated are added two by two, and then passed up until the final result is obtained. Obviously, the structure supports multi-floating point parallel addition, which accelerates the addition operation, but in the carry propagation, it needs to consume a large amount of clock delay, and the operation result and the order of the operand also have a certain relationship, and the precision loss of the operation result is more Big.

Figure 2 shows the structure of the carry-save addition tree. That is, using the structure of the Wallace tree, the part generated by the carry of each stage of the full adder is connected to the upper part of the next stage, and the carry-over is realized by the connection to avoid the complexity. The carry transfer logic reduces the delay of carry transfer. However, this method cannot be directly used for the addition of floating-point numbers, and the order of the operands is different, which may also cause calculation errors.

In addition, in the commonly used algorithms, the accumulation of floating-point addition and floating-point numbers is mostly mixed. This hybrid operation requires the operator to support both operations at the same time, and the operation result is independent of the order of the given operands.

Summary of the invention

(1) Technical problems to be solved

It is an object of the present invention to provide an apparatus and method capable of performing a plurality of floating point numbers addition, which has the advantages of low arithmetic delay and small loss of accuracy.

(2) Technical plan

The present invention provides an apparatus for performing a plurality of floating point number additions, the floating point number including a sign bit, an exponent bit, and a mantissa bit, and the apparatus includes:

a preprocessing module, configured to preprocess the plurality of floating point numbers such that exponential bits and sign bits of the plurality of floating point numbers are consistent;

An adding module, configured to add a plurality of floating-point numbers after the pre-processing, to obtain an accumulated result and a value to be shifted of the accumulated result, where the accumulated result includes a sign bit, an exponent bit, and a mantissa bit;

And a normalization processing module, configured to shift the sign bit, the exponent bit, and the mantissa bit of the accumulated result according to the value to be shifted, to obtain a normalized accumulated result.

Further, the preprocessing module includes:

a comparison selection module, configured to compare the exponential bits of the plurality of floating point numbers in a binary tree to select a maximum exponent bit;

Calculating a shifting module for determining a number n of bits that need to be logically shifted for each floating point number according to a relationship between each floating point number and an exponent bit of a floating point number having a maximum exponent bit, and the mantissa bit of the corresponding floating point number Performing a logical shift such that the exponent bits of each floating point number are equal to the maximum exponent bit, and at the same time, the sign bit of each floating point number is consistent with the sign bit of the largest floating point number of the exponent bit, wherein the floating point number is When changing the sign bit, the mantissa is complemented.

Further, calculating the number of bits n of the logical shift obtained by the shift module includes:

Calculating a difference Δe between the largest exponent bit and the exponent bit of the floating point number to be logically shifted;

If the floating point number with the largest exponent bit is a normalized floating point number and the floating point number to be logically shifted is a non-normalized floating point number, let n = Δe-1; otherwise, let n = Δe.

Further, the shift module calculates a logical shift of the mantissa of the floating point number, including:

Adding a 1-bit hidden bit before the highest bit of the mantissa of the floating-point number, wherein the value of the hidden bit is 1 for the normalized floating-point number, and 0 for the non-normalized floating-point number;

Add k "0"s as the valid bits after the lowest bit of the mantissa of the floating point number;

Shifting the mantissa of the valid and hidden bits to the right by n bits to discard the lowest n bits of the mantissa;

The lowest bit of the shifted mantissa bit is used as a sticky bit, and the sticky bit is ORed with the discarded n bit, and the sticky bit is updated by the operation result to obtain the mantissa bit of the final desired floating point number.

Further, the addition module includes:

The Wallace Tree module is used to add multiple floating point numbers using the Wallace tree structure until it is reduced to two numbers;

The final result accumulating module is configured to add the two numbers to obtain a first accumulated result, and add the inverse codes of the two numbers to obtain a second accumulated result, and select the first according to the highest bit of the first accumulated result. Accumulating the result or the second accumulated result as an accumulated result;

The leading zero prediction module is configured to perform logical operations on the two numbers to determine the position of the first significant digit of the accumulated result to obtain the value to be shifted of the accumulated result. Specifically, suppose the two numbers are A and B, first using the propagation function.

Generate function G=AB, kill function Z=(AB)' to operate on each bit separately; then, set one finger for each bit

Then we can get the positional parameter as

The first position parameter that is not 0 is the position of the first significant digit that is sought, and the lower corner is output in binary form.

Further, the normalization processing module logically shifts the accumulated result according to the value to be shifted, so that the first significant digit of the accumulated result is at the highest position, and normalizes the accumulated result after the logical shift to obtain an accumulated result. Sign bit, exponent bit, and mantissa.

The present invention also provides a method for performing a plurality of floating point number additions, the floating point number including a sign bit, an exponent bit, and a mantissa bit, and the method includes:

S1, preprocessing a plurality of floating point numbers to make the exponential bits and the sign bits of the plurality of floating point numbers coincide;

S2, adding a plurality of floating-point numbers after the pre-processing to obtain an accumulated result and a value to be shifted of the accumulated result, where the accumulated result includes a sign bit, an exponent bit, and a mantissa bit;

S3, shifting the sign bit, the exponent bit and the mantissa bit of the accumulated result according to the value to be shifted, to obtain a normalized accumulated result.

Further, step S1 includes:

S11, comparing the exponential bits of the plurality of floating point numbers in the form of a binary tree to select the largest exponential bit;

S12. Determine, according to the relationship between each floating point number and an exponent bit of the floating point number having the largest exponent bit, a bit number n that needs to be logically shifted for each floating point number, and logically shift the mantissa bit of the corresponding floating point number. So that the exponent bits of each floating point number are equal to the maximum exponent bit, and at the same time, the sign bit of each floating point number is consistent with the sign bit of the largest floating point number of the exponent bit, wherein when the floating point number changes the sign bit, Complement the code for its mantissa.

Further, in step S12, the number of bits n of the logical shift is obtained, including:

Further, in step S12, logically shifting the mantissa bits of the floating point number includes:

The first bit is padded before the highest bit of the mantissa of the floating point number, wherein the value of the hidden bit is 1 for the normalized floating point number and 0 for the non-normalized floating point number;

Further, step S2 includes:

S21, using a Wallace tree structure to add a plurality of floating point numbers until they are reduced to two numbers;

S22, adding the two numbers to obtain a first accumulated result, and adding the inverse codes of the two numbers to obtain a second accumulated result, and selecting the first accumulated result according to the sign bit of the floating point number with the largest exponent bit. Or a second accumulated result as the accumulated result;

S23, performing logical operations on the two numbers to determine the first significant digit of the accumulated result The position to get the value to be shifted of the accumulated result.

Further, step S3 includes: logically shifting the accumulated result according to the value to be shifted of the accumulated result, so that the first significant digit of the accumulated result is at the highest position, and normalizing the accumulated result after the logical shift, The sign bit, exponent bit, and mantissa bit of the accumulated result are obtained.

(3) Beneficial effects

The invention can add multiple floating point numbers of the same standard, solves the problem of adding operations of multiple operands in one operation, and adds effective digital bits and sticky bits to reduce the precision loss of the operation result; The calculation of the structure such as the tree reduces the complexity of the hardware and improves the operation speed.

DRAWINGS

FIG. 1 is a schematic structural diagram of a serial carry addition tree in the prior art.

2 is a schematic view showing the structure of a Wallace tree in the prior art.

3 is a schematic diagram of an apparatus for performing multiple floating point number additions provided by the present invention.

Figure 4 is a schematic illustration of the comparison of index points in the present invention.

Figure 5 is a schematic illustration of the selection of the maximum index bit in the present invention.

Figure 6 is a schematic diagram of a calculation shifting module in the present invention.

Figure 7 is a schematic illustration of the final result accumulation module of the present invention.

detailed description

The present invention will be further described in detail below with reference to the specific embodiments of the invention.

3 is a schematic diagram of an apparatus for performing multiple floating point number addition according to the present invention. As shown in FIG. 3, the apparatus includes a preprocessing module, an adding operation module, and a normalization processing module. The preprocessing module includes a comparison selection module and a calculation shift. The bit module, the addition module includes a Wallace tree module, a final result accumulation module, and a leading zero prediction module.

There are x identical y-bit floating point numbers of the same standard, and the i-th floating-point number is represented by f _i , where x, y, and i are both positive integers, and 1 ≤ i ≤ x.

In the preprocessing module, each floating point number f _{i is} split into a sign bit portion s _i , an exponent bit portion e _i and a mantissa bit portion m _i , that is, f _i =(s _i , e _i , m _i ). The comparison selection module performs a pairwise selection comparison operation, as shown in FIG. 4, that is, if e _a >e _b , then a is selected, otherwise b is selected. Then, as shown in FIG. 5, using the binary tree structure, the floating point number f _max having the largest exponent bit is sequentially selected, and the sign bit, the exponent bit, and the mantissa are s _max , e _max , m _{max , respectively} .

6 is a schematic diagram of the calculation shifting module in the present invention, that is, the difference Δe of the index of each floating point number f _i and the floating point number f _max of the maximum exponent bit is respectively determined. If f _max is a normalized floating point number and f _{i is a} non-normalized floating point number, then the number of bits that logically shift the mantissa portion of f _i is n = Δe-1; otherwise, n = Δe. The mantissa portion m _i of each floating point number f _i is then logically shifted accordingly. After the shift operation ends, the exponent bits corresponding to the x floating point numbers are the same, and the mantissa bits can be directly calculated. The specific operation is to first fill the top bit of the mantissa m _i with a hidden bit. When the floating point number f _i is a normalized floating point number, the value of the hidden bit is 1; when the floating point number f _{i is} non-specific When floating point numbers are used, the hidden bit is 0. After the lowest digit of the mantissa bit, add k "0"s as valid bits. At this time, the total number of digits of the mantissa is equal to the total number of bits after shifting, that is, the number of digits of the original mantissa + the number of hidden digits + the number of significant digits added Then, each floating point number f _i is shifted according to the previously obtained number of bits to be logically shifted, where n bits are shifted right first to discard the lowest n bits of the mantissa bit; then the shifted mantissa bit is shifted The lowest bit is used as the sticky bit, and the “n” operation is performed with the discarded n bits, and the operation result is updated to the value of the sticky bit to obtain the final result of the desired shifted mantissa bit. Finally, it is judged whether the sign bit portion s _{i of} each floating point number f _i is the same as the sign bit portion s _max of the floating point number f _max of the maximum exponent bit, and the same does not require any operation, and the difference is obtained by taking the mantissa portion as a complement. The latter is directly operated by the adder.

In the addition module, using the Wallace tree structure shown in Figure 2, the mantissas of the shifted floating point numbers are added until they are reduced to two numbers, denoted as sum ₁ and carry ₁ , and output to The final result is the accumulation module and the leading zero prediction module. The Wallace tree structure quickly sums up the processed multiple floating point numbers into two numbers by simple hardware, that is, each time using i full adders, the j i-bit numbers are added and converted into The number of 2*j/3 i+1 bits is added, and then converted into 4*j/9 numbers by a full-adder, until it is converted into 2 numbers.

The final result accumulation module uses two channels to calculate the operation result. The structure is shown in Fig. 7. Adding _a sum of a path ₁ and directly with Carry, other path of the two counter-code addition, according to the most significant bit last results obtained in the first passage, if the most significant bit is 0, the choice of The result of one path is output as the final result tmp_sum of the accumulated portion, otherwise, the result of the second path is selected as the final result tmp_sum of the accumulated portion and output. The leading zero prediction module uses the leading zero anticipator (LZA) method to first obtain the propagation function of the input sum ₁ and carry ₁ in bits.

Generate the function G=sum ₁ · carry ₁ , kill the value of the function Z=(sum ₁ · carry ₁ )'; then, find each

You can get the positional parameter as

The value of the lower corner of the first position parameter that is not 0 is the position num_shift of the first significant digit of the final result tmp_sum of the cumulative part we are looking for, and it can be output in binary form.

In the normalization processing module, the final result tmp_sum is logically shifted according to the position num_shift of the first significant digit of the leading zero prediction module, the number of bits is num_shift, and then normalized to obtain the sign bit of the final result. s _result , exponent bit e _result and mantissa bit m _result , , combined to get the final result sum _result ={s _result ,e _result ,m _result }.

The present invention provides an embodiment in which four 16-bit floating point numbers are added, that is, x=4 and y=16. Among them, the floating-point number standard adopts IEEE754's half-type floating-point number standard, that is, each floating-point number is composed of 1 bit symbol bit, 5 bit exponent bit and 10 bit mantissa bit.

In the apparatus shown in FIG. 3, four floating-point numbers are input and expressed in binary as f ₁ =0001001010000001, f ₂ =0001110011110000, f ₃ =00011001011111111,f ₄ =0010010011011001, split into sign bit, exponent bit, mantissa bit The format, ie {s,e,m}, is expressed in binary to get f ₁ ={0,00100,1010000001},f ₂ ={0,00111,0011110000},f ₃ ={0,00110,01011111111},f ₄ = {0, 01001, 0011011001}. Using the apparatus shown in FIG. 4, the exponential bits e ₁ = 00100 and e ₂ = 00111 of f ₁ and f ₂ are respectively compared, and a larger index value e _{max (e1, e2)} = 00111 is selected, and f _{3 is} compared. The index bits of f ₄ are e ₃ =00110, e ₄ =01001, and a larger index value e _{max(e3, e4)} =01001 is selected, and then e _{max(e1, is} compared using a tree structure as shown in FIG. 5 _{. E2)} =00111 and e _max(e3,e4) =01001, and a larger exponent bit e _max =01001 is selected, which is represented by f _max =f ₄ =0010010011011001, and the sign bit and the mantissa are respectively s _max = 0 and m _max = 0011011001.

Then, the difference between the exponent bits e ₁ , e ₂ , e ₃ , e ₄ and e _max of f ₁ , f ₂ , f ₃ , and f ₄ is obtained, respectively, Δe ₁ =5, Δe ₂ = 2, Δe ₃ = 3. Δe ₄ =0. Since f ₁ , f ₂ , f ₃ , and f ₄ are normalized floating point numbers, the number of bits to be shifted is n = Δe, that is, n ₁ = Δe ₁ = 5, n ₂ = Δe ₂ = 2, n ₃ = _{_{Δe 3 = 3, n 4 =}} Δe 4 = 0. Here, in order to reduce the precision loss in the operation process, three significant digits are added, that is, k=3, and the lowest bit is a sticky bit. When shifting, since this embodiment adopts the IEEE754 standard, first the first bit of the mantissa portion of f _max , f ₁ , f ₂ , f ₃ , and f ₄ is padded with 1 hidden bit, and it is judged whether or not they are normalized. Floating point number. Since f ₁ , f ₂ , f ₃ , and f ₄ are normalized floating point numbers, that is, the values of hidden bits of f _max , f ₁ , f ₂ , f ₃ , and f ₄ are 1. Then, the last digit of the mantissa is followed by 3 "0"s, that is, the preset total number of digits is reached: the original mantissa + the hidden digits + the new significant digits = 10 + 1 + 3 = 14 bits, then, shift right according to the index difference n, discard the lowest n bits; OR the value of the discarded n bits with the last bit of the sticky bit, and update the value of the sticky bit with the operation result to obtain The final result of the desired mantissa after the shift. Taking f ₁ as an example, the mantissa part of the above is 1010000001, and the highest bit is increased by one hidden bit. Since f ₁ is a normalized floating point number, the value of the hidden bit is 1 and 11010000001 is obtained; Three 0s, and the lowest bit is defined as the sticky bit, which gives 11010000001000. Since n ₁ =5, we need to move 5 bits, so the rightmost 5 bits 01000 need to be discarded, get 00000110100000; the discarded 5 digit 01000 and the sticky bit 0 are ORed to get 1, The result is updated with the result, that is, the value of the sticky bit is 1 and the result after shifting is 00000110100001. Taking f ₂ as an example, the mantissa part of the above is 0011110000, and the highest bit is increased by one hidden bit. Since f ₂ is a normalized floating point number, the value of the hidden bit is 1, and 3 bits are added after the lowest bit. 0, and define the lowest bit as the sticky bit, get 10011110000000. Since n ₂ = 2, we need to move 2 bits, so the rightmost 2 bits 00 need to be discarded to get 00100111100000; the discarded 2 digit 00 and the sticky bit 0 are ORed to get 0. The sticky bit is updated with the result, that is, the value of the sticky bit is 0, and the result of the shift is 00100111100000. Finally, the sign bits s ₁ , s ₂ , s ₃ , s ₄ and s _max of the floating point numbers f ₁ , f ₂ , f ₃ , and f ₄ are compared, and the results are all 0, that is, both are positive numbers, so no need to The mantissa part is then replenished.

As shown in FIG. 3, the result of the preprocessing is input to the addition module. Four 14-bit preprocessed mantissas are processed using the Wallace tree structure shown in FIG. Here, the present invention contemplates the use of a two-level Wallace tree structure, first by adding a first-level 4-2 Wallace tree structure, and then inputting the results separately to the second-level 3-2 Wallace tree structure. Operates with the leading zero prediction part. 3-2 Wallace tree will eventually return the result to two numbers, namely sum ₁ =11011000000100 and carry ₁ =110100010, and output to the final result accumulation. In this part, the operation result is calculated by using two paths, one channel directly sums sum ₁ and carry ₁ , and the other path reverses the two, and then adds. Since the highest bit of the result of the first path is 0, the result of obtaining the first path is selected as the final result of the accumulated part, that is, tmp_sum=0011100101001000, and is output to the third module. The leading zero prediction part is to calculate the output result of the first stage 4-2 Wallace tree by using the leading zero prediction algorithm (LZA algorithm) to calculate the final result of the accumulated part. The number of bits to be moved is expressed in binary as num_shift=10. Output to the third module. Among them, the leading zero prediction part and the second level Wallace tree part are executed in parallel.

As shown in FIG. 3, the normalization processing module uses the LZA algorithm to perform logical operations according to tmp_sum and f _max obtained by the first module, to obtain a sign bit s _result =0 of the final result; f _max and second obtained according to the first module. The tmp_sum obtained by the module accumulation portion and the output result num_shift of the leading zero prediction portion are logically operated to obtain an exponential bit e _result =01001 of the final result; the output result num_shift of the leading zero prediction portion, and the f _max pair obtained by the first module are second. The tmp_sum obtained by the module is shifted and normalized to obtain the mantissa of the final result m _result =11001100101001. Finally, combine the three to get the final result sum _result ={s _result ,e _result ,m _result }={0,01001,11001100101001}=00100111001100101001.

In summary, the addition operation of multiple floating-point numbers of the same standard can be completed quickly and efficiently, the number of operands supported by one operation is increased, the operation delay is reduced, the operation process is accelerated, and the precision loss of the operation result is reduced.

The specific embodiments of the present invention have been described in detail, and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Claims

A device for performing a plurality of floating point number additions, the floating point number comprising a sign bit, an exponent bit and a mantissa bit, wherein the device comprises:

a preprocessing module, configured to preprocess the plurality of floating point numbers such that exponential bits and sign bits of the plurality of floating point numbers are consistent;

An adding module, configured to add a plurality of floating-point numbers after the pre-processing, to obtain an accumulated result and a value to be shifted of the accumulated result, where the accumulated result includes a sign bit, an exponent bit, and a mantissa bit;

And a normalization processing module, configured to shift the sign bit, the exponent bit, and the mantissa bit of the accumulated result according to the value to be shifted to obtain a normalized accumulated result.
The apparatus for performing a plurality of floating point number additions according to claim 1, wherein the preprocessing module comprises:

a comparison selection module, configured to compare the exponential bits of the plurality of floating point numbers in a binary tree to select a maximum exponent bit;

Calculating a shifting module for determining a number n of bits that need to be logically shifted for each floating point number according to a relationship between each floating point number and an exponent bit of a floating point number having a maximum exponent bit, and the mantissa bit of the corresponding floating point number Performing a logical shift such that the exponent bits of each floating point number are equal to the maximum exponent bit, and at the same time, the sign bit of each floating point number is consistent with the sign bit of the largest floating point number of the exponent bit, wherein the floating point number is When changing the sign bit, the mantissa is complemented.
The apparatus for performing a plurality of floating point number additions according to claim 2, wherein the calculating the shifting block to determine the number of bits n of the logical shift comprises:

Calculating a difference Δe between the largest exponent bit and the exponent bit of the floating point number to be logically shifted;

If the floating point number with the largest exponent bit is a normalized floating point number and the floating point number to be logically shifted is a non-normalized floating point number, let n = Δe-1; otherwise, let n = Δe.
The apparatus for performing a plurality of floating point number additions according to claim 3, wherein the calculating the shifting module logically shifting the mantissa bits of the floating point number comprises:

Adding a 1-bit hidden bit before the highest bit of the mantissa of the floating-point number, wherein the value of the hidden bit is 1 for the normalized floating-point number, and 0 for the non-normalized floating-point number;

Adding k “0”s as the effective bits after the lowest bit of the mantissa of the floating point number;

Shift the n-bit of the significant digit and the hidden digit to the right by n bits to discard the lowest n-bit of the mantissa;

The lowest bit of the shifted mantissa bit is used as a sticky bit, and the sticky bit is ORed with the discarded n bit, and the sticky bit is updated by the operation result to obtain the mantissa bit of the final desired floating point number.
The apparatus for performing a plurality of floating point number additions according to claim 1, wherein the adding module comprises:

a Wallace tree module for adding the plurality of floating point numbers using a Wallace tree structure until the two numbers are reduced;

The final result accumulating module is configured to add the two numbers to obtain a first accumulated result, and add the inverse codes of the two numbers to obtain a second accumulated result, and select the first according to the highest bit of the first accumulated result. An accumulated result or a second accumulated result as the accumulated result;

The leading zero prediction module is configured to perform logical operations on the two numbers to determine a position of the first significant digit of the accumulated result to obtain a value to be shifted of the accumulated result.
The apparatus for performing a plurality of floating point number additions according to claim 5, wherein said normalization processing module logically shifts said accumulation result according to said value to be shifted, so that said said The first significant digit of the accumulated result is at the highest bit, and the accumulated result after the logical shift is normalized to obtain the sign bit, exponent bit, and mantissa of the accumulated result.
A method for performing a plurality of floating point numbers, the floating point number comprising a sign bit, an exponent bit, and a mantissa bit, wherein the method comprises:

S1, preprocessing the plurality of floating point numbers such that exponential bits and sign bits of the plurality of floating point numbers are consistent;

S2, adding a plurality of floating-point numbers after the pre-processing to obtain an accumulated result and a value to be shifted of the accumulated result, where the accumulated result includes a sign bit, an exponent bit, and a mantissa bit;

S3, shifting the sign bit, the exponent bit, and the mantissa bit of the accumulated result according to the value to be shifted to obtain a normalized accumulated result.
The method for performing a plurality of floating point number additions according to claim 7, wherein the step S1 comprises:

S11, comparing the exponential bits of the plurality of floating point numbers in the form of a binary tree, and selecting the largest exponent bit;

S12. Determine, according to the relationship between each floating point number and an exponent bit of the floating point number having the largest exponent bit, a bit number n that needs to be logically shifted for each floating point number, and logically shift the mantissa bit of the corresponding floating point number. So that the exponent bits of each floating point number are equal to the maximum exponent bit, and at the same time, the sign bit of each floating point number is consistent with the sign bit of the largest floating point number of the exponent bit, wherein when the floating point number changes the sign bit, Complement the code for its mantissa.
The method for performing a plurality of floating point number additions according to claim 8, wherein in step S12, the number of bits n of the logical shift is obtained, including:

Calculating a difference Δe between the largest exponent bit and the exponent bit of the floating point number to be logically shifted;

If the floating point number with the largest exponent bit is a normalized floating point number and the floating point number to be logically shifted is a non-normalized floating point number, let n = Δe-1; otherwise, let n = Δe.
The method for performing a plurality of floating point number additions according to claim 8, wherein in step S12, logically shifting the mantissa bits of the floating point number comprises:

Adding a 1-bit hidden bit before the highest bit of the mantissa of the floating-point number, wherein the value of the hidden bit is 1 for the normalized floating-point number, and 0 for the non-normalized floating-point number;

Adding k “0”s as the effective bits after the lowest bit of the mantissa of the floating point number;

Shifting the mantissa of the valid and hidden bits to the right by n bits to discard the lowest n bits of the mantissa;

The lowest bit of the shifted mantissa bit is used as a sticky bit, and the sticky bit is ORed with the discarded n bit, and the sticky bit is updated by the operation result to obtain the mantissa bit of the final desired floating point number.
The method for performing a plurality of floating point number additions according to claim 7, wherein the step S2 comprises:

S21, adding the plurality of floating point numbers by using a Wallace tree structure until the two numbers are reduced;

S22, adding the two numbers to obtain a first accumulated result, and adding the inverse codes of the two numbers to obtain a second accumulated result, and selecting the first accumulated result or the first according to the highest bit of the first accumulated result Two accumulated results as the accumulated result;

S23, performing logical operations on the two numbers to determine a position of the first significant digit of the accumulated result to obtain a value to be shifted of the accumulated result.
The method for performing a plurality of floating point number additions according to claim 11, wherein the step S3 comprises: logically shifting the accumulated result according to the value to be shifted of the accumulated result, The first significant digit of the accumulated result is placed in the highest bit, and the accumulated result after the logical shift is normalized to obtain a sign bit, an exponent bit, and a mantissa bit of the accumulated result.