FR3094560A1 - Contact on germanium - Google Patents

Abstract

Germanium Contact The present description relates to a method of forming an electrical contact (400) with a semiconductor region (110) consisting mainly of germanium, comprising forming a first region (420) consisting of a first intermetallic material in which more than 70% of the non-metallic atoms are silicon. The present description also relates to a device comprising such a contact point. Figure for the abstract: Fig. 4

Description

Germanium handshake

The present description generally relates to electronic devices, and more particularly to electronic components comprising germanium and to methods of manufacturing electronic components.

Some electronic components, such as transistors, diodes, etc., use the properties of germanium. For example, a PIN type photodiode, that is to say a photodiode comprising an intrinsic semiconductor region between doped N and P type semiconductor regions, can be based on germanium. The photodiode can then detect optical radiation with a wavelength of between 0.9 μm and 1.5 μm.

In such a component, a region comprising germanium is intended to be electrically connected to other devices by a conductive link. The electrical contact between this region and the conductive connection is ensured by a contact zone, or contact point.

There is a need to reduce the resistances and/or to increase the reliability of the known contacts on a semiconductor region comprising germanium.

There is a need to simplify the known methods of making contacts on a semiconductor region comprising germanium.

One embodiment overcomes all or part of the drawbacks of known contact points with a semiconductor region comprising germanium.

One embodiment overcomes all or part of the drawbacks of known methods for making contact with a semiconductor region comprising germanium.

Thus, one embodiment provides a method of forming an electrical contact with a semiconductor region consisting primarily of germanium, comprising forming a first zone consisting of a first intermetallic material in which more than 70% of the atoms non-metallic are silicon.

One embodiment provides an electronic device comprising a semiconductor region consisting mainly of germanium, and an electrical contact point with the semiconductor region, the contact point comprising a first zone consisting of a first intermetallic material in which more than 70% of the non-metal atoms are silicon.

According to one embodiment, the contact point comprises, between the first zone and the semiconductor region, a second zone consisting of a second intermetallic material in which the non-metallic atoms are mainly germanium.

According to one embodiment, the metal atoms of each of the first and second intermetallic materials are mainly nickel.

According to one embodiment, each of the first and second intermetallic materials comprises platinum and/or cobalt.

According to one embodiment, the first intermetallic material comprises germanium.

According to one embodiment, the formation of the first zone successively comprises: a) the formation of at least one semiconductor layer covering the semiconductor region and comprising at least 70% of silicon atoms; b) forming a metallic region on said at least one semiconductor layer; and c) reacting the metallic region with at least a portion of said at least one semiconductor layer.

According to one embodiment, the method further comprises reacting the material of the metallic region with that of the semiconductor region.

According to one embodiment, step c) comprises: a first heat treatment, preferably at a temperature below 300° C.; removing portions of the metal region unreacted during the first heat treatment; and a second heat treatment, preferably at a temperature between 390°C and 420°C.

According to one embodiment, the method comprises, before step b), the formation of a protective layer, preferably of titanium nitride, on the metallic region.

According to one embodiment, the method comprises the formation successively: of an additional semiconductor layer comprising at least 70% of silicon atoms; an insulating layer covering the additional semiconductor layer; and an opening passing through the insulating layer and the additional semiconductor layer, said at least one semiconductor layer being formed in the opening and forming, with the parts of the additional semiconductor layer located around the opening, a continuous layer.

According to one embodiment, the method successively comprises the formation: of a multilayer of first semiconductor layers comprising at least 70% of silicon atoms alternated with second semiconductor layers consisting mainly of germanium; an insulating layer covering the multilayer; and an opening passing through the insulating layer and part of the multilayer, said at least one semiconductor layer consisting of the first layers having been left intact under the opening.

According to one embodiment, the multilayer is monocrystalline.

Another embodiment provides a method for manufacturing an electronic device, comprising the implementation of a method as defined above.

Another embodiment provides a photodiode comprising a device as defined above or a device obtained by a method as defined above.

These characteristics and advantages, as well as others, will be set out in detail in the following description of particular embodiments given on a non-limiting basis in relation to the attached figures, among which:

Figure 1 is a sectional view, partial and schematic, representing a step of a first embodiment of a method of manufacturing a contact;

Figure 2 is a sectional view, partial and schematic, representing another step of the first embodiment;

Figure 3 is a sectional view, partial and schematic, representing another step of the first embodiment;

Figure 4 is a sectional view, partial and schematic, representing another step of the first embodiment;

FIG. 5 is a partial and diagrammatic sectional view representing a step of a second embodiment of a method of manufacturing a contact plug;

Figure 6 is a sectional view, partial and schematic, representing another step of the second embodiment;

Figure 7 is a sectional view, partial and schematic, representing another step of the second embodiment;

FIG. 8 is a partial and diagrammatic sectional view representing a step of a third embodiment of a method of manufacturing a contact plug;

Figure 9 is a sectional view, partial and schematic, representing another step of the third embodiment; and

FIG. 10 is a partial and schematic sectional view showing another step of the third embodiment.

The same elements have been designated by the same references in the various figures. In particular, the structural and/or functional elements common to the various embodiments may have the same references and may have identical structural, dimensional and material properties.

For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been represented and are detailed. In particular, in the electronic components, the elements other than a semiconductor region comprising germanium, a contact, and an electrical conductor, have not been described, the embodiments being compatible with the known electronic components comprising a germanium region.

Unless otherwise specified, when reference is made to two elements connected together, it means directly connected without intermediate elements other than conductors, and when reference is made to two elements connected or coupled together, it means that these two elements can be connected or be linked or coupled through one or more other elements.

In the following description, when referring to absolute position qualifiers, such as "front", "rear", "up", "down", "left", "right", etc., or relative, such as the terms "above", "below", "upper", "lower", etc., or to qualifiers of orientation, such as the terms "horizontal", "vertical", etc., it reference is made unless otherwise specified to the orientation of the figures.

Unless specified otherwise, the expressions “about”, “approximately”, “substantially”, and “of the order of” mean to within 10%, preferably within 5%.

FIGS. 1 to 4 are partial and schematic cross-sectional views representing steps of an embodiment of a method of manufacturing a contact point on a region comprising germanium.

The method is implemented during the manufacture of an electronic device comprising one or more components comprising germanium or based on germanium. The device may comprise, or consist of, an integrated circuit electronic chip. Such a chip is defined by a portion of semiconductor wafer and elements, such as electronic components, entirely located in and on one face of the wafer. In particular, the method can be implemented for the manufacture of a photodiode comprising germanium.

At the stage of FIG. 1, a substrate 100 is provided. The substrate 100 can be constituted by a portion of a semiconductor wafer, for example made of germanium. The substrate 100 can also be constituted by a layer covering the upper face of a support such as, for example, a semiconductor wafer.

A semiconductor region 110 comprising germanium is located on the side of one face of the substrate 100, for example the front or upper face of the substrate 100. In the case where the substrate 100 comprises, or consists of, germanium, the region 110 is for example a doped region of the substrate. In the case where the substrate 100 is made of a semiconductor other than germanium, for example silicon, the semiconductor region 110 may have been formed for example in a cavity etched in the substrate 100. Preferably, the semiconductor region 110 is monocrystalline, the substrate 100 preferably being monocrystalline. Semiconductor region 110 can then result from epitaxy.

The region 110 consists mainly, that is to say mainly, of germanium. In other words, region 110 is made of a semiconductor material having an atomic percentage of germanium greater than 50%, preferably greater than 90%. In a preferred example, region 110 consists of germanium, for example doped. More preferably, region 110 is made of monocrystalline germanium. In another example, region 110 is made of silicon-germanium, for example doped.

Is formed on the semiconductor region 110, a semiconductor layer 120 having an atomic percentage of silicon greater than 70%. Layer 120 may comprise, in addition to silicon, a metalloid other than silicon, preferably germanium. In a preferred example, layer 120 is made of silicon. In another example, layer 120 is made of silicon-germanium.

Preferably, the semiconductor layer 120 is monocrystalline. For this, the layer 120 can be obtained by epitaxy on the monocrystalline region 110. The thickness of the semiconductor layer 120 is less than a thickness threshold allowing the epitaxial layer to be monocrystalline. This thickness threshold can be determined experimentally as a function of the composition of the semiconductor layer 120 and of the semiconductor region 110. This threshold is of the order of 2 nm for a layer 120 of silicon epitaxied on the region 110 of germanium. Alternatively, the semiconductor layer 120 is not monocrystalline. The thickness of the layer 120 can then be greater than the thickness threshold.

A metal layer 130 is then formed covering the semiconductor layer 120. Preferably, the metal layer 130 comprises nickel, for example substantially consists of nickel, for example consists of nickel. Preferably, layer 130 comprises, in addition to nickel, platinum and/or cobalt. In a preferred example, the metal of layer 130 comprises, more preferably consists of, nickel and cobalt, the atomic percentage of the cobalt being between 5 and 20%. In another preferred example, the metal of layer 130 comprises, more preferably consists of, nickel and platinum, the atomic percentage of platinum being between 5 and 15%.

Preferably, the thickness of the metal layer 130 is greater than half that of the semiconductor layer 120. More preferably, the metal layer 130 has a thickness comprised between 7 and 50 nm.

Preferably, before the deposition of the metallic layer 130, the upper surface of the semiconductor layer 120 has previously been prepared. The surface preparation step comprises, for example, a liquid phase treatment based on hydrofluoric acid. , followed by plasma treatment. The plasma can be based on argon, or, for example, of the type known under the trade name SiconiTM. The plasma treatment and the deposition of the metal layer 130 are then carried out successively without breaking the vacuum. This makes it possible to avoid the presence of impurities, such as oxides, between the semiconductor 120 and metallic 130 layers. Such impurities could come from exposure to air after the layer 120 deposition step, or after the liquid phase surface preparation step. The semiconductor 120 and metal 130 layers are therefore directly in contact with each other.

Preferably, after the formation of the metallic layer 130, a protective layer 140 is formed on the layer 130. This layer is then preferably formed without breaking the vacuum after the deposition of the metallic layer 130. The layer 140 is intended to protect the structures below the layer 140 against oxidation during subsequent process steps. Preferably, the protective layer 140 is made of titanium nitride. Alternatively, the protective layer 140 can be omitted.

In the step of FIG. 2, a first heat treatment is carried out. More precisely, this heat treatment corresponds to an annealing of the structure obtained in FIG. 1. This first heat treatment is carried out at a temperature making it possible to partially react the metal of the metallic layer 130 with the material of the semiconductor layer 120. thus obtains a layer 220 instead of the layer 120. The temperature of the first heat treatment is preferably less than or equal to 300° C., for example between 250° C. and 300° C., which allows a partial reaction of the layer 130 comprising nickel with the material of the semiconductor layer 120.

Preferably, the first heat treatment is carried out in the presence of nitrogen. The dinitrogen is preferably at atmospheric pressure or at a pressure less than 1 bar above atmospheric pressure. The duration of the first heat treatment is preferably between 10 s and 120 s.

The layer 220 comprises, preferably consists of, an intermetallic material, or intermetallic compound, that is to say the combination of one or more metallic chemical elements and one or more chemical elements, typically metalloids, which can enter into the composition of a semiconductor. Preferably, the intermetallic material has a crystalline structure combining metallic and non-metallic chemical elements. In the layer 220, the non-metallic chemical elements are substantially constituted by the material of the semiconductor layer 120. In particular, the fact that more than 70% of the atoms of the semiconductor layer 120 are silicon implies that more than 70% of the atoms not layers of layer 220 are silicon. In a preferred example, the intermetallic material of layer 220 is a nickel silicide or a silicide comprising nickel. In another preferred example, the intermetallic material of layer 220 is a nickel germano-silicide or a germano-silicide comprising nickel.

Preferably, the thickness of the metallic layer 130 chosen in the step of FIG. 1 is sufficient for a part of the metal of the layer 130 to react with an upper part of the semiconductor region 110. This reaction produces a layer 210 located under layer 220. Layer 210 preferably comprises an intermetallic material. Because region 110 is primarily germanium, the non-metallic atoms in layer 210 are primarily germanium atoms. Thus, when the metallic layer 130 is made of nickel or comprises nickel, the intermetallic material of the layer 210 is made of nickel germanide or a germanide comprising nickel.

Preferably, the thickness of the metallic layer 130 chosen in the step of FIG. 1 is sufficient for a part 230 of the metallic layer 130 not to react with the semiconductor layer 120 and the semiconductor region 110.

At the step of FIG. 3, the possible protective layer 140 is removed, as well as the part 230 of the layer 130 which has not reacted. This removal is selective with respect to the material of the layer 220. The removal is for example carried out in an etching solution based on sulfuric acid and hydrogen peroxide, or even for example in an etching solution with based on hydrochloric acid and nitric acid. Because the layer 220 comprises, apart from the metallic elements, more than 70% of silicon atoms, these solutions make it possible to etch the materials of the layers 130 and 140 without removing or altering the layer 220.

At the step of FIG. 4, a second heat treatment is carried out. This heat treatment corresponds to an annealing of the structure obtained in the step of FIG. 3. This transforms the layers 210 and 220 into respective layers 410 and 420.

When layer 130 comprises nickel, the heat treatment temperature is preferably greater than or equal to 390°C. This allows that, after the second heat treatment, the phase of the intermetallic material of the layer 420 has an electrical resistivity lower than that of the other phases of this intermetallic. In particular, this allows the layer 420 to comprise the same proportion of metallic atoms as of non-metallic atoms, for example to comprise the same atomic proportions of nickel and of silicon (NiSi). By way of example, part of the nickel contained in the layer 220 at the step of FIG. 3 reacts with the semiconductor region 110 during the second anneal. The thickness of layer 410 is then greater than that of layer 210 (FIGS. 2 and 3). Alternatively, layer 210 is not formed during the first heat treatment, and only layer 410 is formed during the second heat treatment. The fact, mentioned above, that at the step of FIG. 1 the thickness of the metallic layer 130 is preferably greater than half that of the semiconductor layer 120, makes it possible to obtain the layer 410 during the second heat treatment.

Further, when layer 130 comprises nickel, the heat treatment temperature is preferably less than 420°C. This makes it possible to optimize the resistivity of the nickel germanide of the layer 410, and to avoid deteriorating this resistivity by too high a temperature.

The intermetallic zones defined by the layers 410 and 420 thus obtained constitute an electrical contact point 400 on the semiconductor region 110.

One could have thought of forming a contact not comprising the layer 420. For this, one could have imagined implementing steps similar to those of FIGS. 1 to 4, but without forming the layer 120 of silicon. However, during a step, such as that of Figure 3, of removing part of an unreacted metal layer, contact between the germanium and an etching solution would have risked oxidizing the germanium. and dissolving the germanium oxide in the solution. This would have damaged the semiconductor region 110. This would have resulted in reliability and contact resistance issues.

Thus, the presence of the layer 420 makes it possible to obtain a contact point 400 on the germanium having better resistivity and reliability than a contact point without such a layer.

FIGS. 5 to 7 are partial and schematic cross-sectional views representing steps of another embodiment of a method of manufacturing a contact point on a semiconductor region 110 comprising germanium. The semiconductor region 110 is identical or similar to that described in relation to FIG. 1, and is preferably located in the upper part of a substrate 100.

In the step of FIG. 5, a semiconductor layer 500 comprising silicon is preferably formed on the upper surface of the semiconductor region 110. Layer 500 is made of silicon, or has an atomic percentage of silicon greater than 70%. By way of example, layer 500 is grown by epitaxy on the surface of semiconductor region 110. The thickness of layer 500 is for example between 1 nm and 3 nm, preferably of the order of 2 nm .

An electrically insulating layer 510 is then formed on the semiconductor layer 500. The insulating layer 510 can be made of silicon dioxide, preferably resulting from a hydrolysis of tetraethyl orthosilicate (TEOS). Preferably, the thickness of the insulating layer 510 is of the order of, or greater than, 100 nm.

At the stage of FIG. 6, an opening 600 passing through the insulating layer 510 right through at the location of the future contact is etched. Preferably, the opening 600 is made only above a part of the semiconductor region 110. The width of the opening can be between 300 nm and 1.5 μm. The opening 600 is compatible with any usual process for obtaining an opening in an insulating layer, for example photolithography followed by plasma etching (the etching mask is not shown). In practice, opening 600 is extended through layer 500 to a level located in semiconductor region 110. 100, between the bottom 602 of the opening 600 and the upper face 604 of the semiconductor layer 500, is for example between 5 nm and 30 nm, preferably of the order of 10 nm.

A semiconductor layer 120A is then grown by epitaxy. Layer 120A is identical in composition and thickness to semiconductor layer 120 of the method of Figures 1 to 4. upper layer 604 of layer 500. As a result, the semiconductor region defined by layer 120A forms, with the remaining portions of layer 500, a continuous semiconductor layer, that is to say devoid of openings, covering the region semiconductor 110, this continuous layer comprising at least 70% silicon.

After that, the metallic layers 130 and optionally the protective layers 140 described in relation to FIG. 1 are successively formed. The layers 130 and 140 cover the bottom of the opening 600 and the remaining portions of the insulating layer 510. Preferably, the total thickness of the metal 130 and protective 140 layers is less than that of the insulating layer 510. In the example shown, the metal 130 and protective 140 layers are formed by non-conformal deposition, that is to say that the materials of these layers are deposited only on the surfaces facing upwards. Because the thickness of the metallic layer 130 is less than that of the insulating layer 510, a metallic region 130A results without contact with the rest of the layer 130, and located at the bottom of the opening 600. The step described here is not limiting, and any method can be used that makes it possible to form a metal region 130A on only part of the semiconductor region 110. As a variant, the metal 130 and/or protective layers 140 can be formed by conformal deposition .

At the step of FIG. 7, the steps of FIGS. 2 to 4 are implemented, namely, successively, the first heat treatment, the removal of any protective layer 140 and of the remaining portions of the metallic layer 130 , and the second heat treatment. This results, on the region 110 consisting mainly of germanium, in a contact point comprising an intermetallic zone 420 formed from the semiconductor layer 120A. Of the non-metallic atoms in the 420 region, more than 70% are silicon atoms. Preferably, as for the layer 420 of FIG. 4, the non-metallic atoms of the zone 420 are silicon atoms. More preferably, zone 420 comprises nickel silicide.

Preferably, as for the process of FIGS. 1 to 4, the thickness of the metallic layer 130 is chosen to be sufficiently thick to form, under the zone 420, an intermetallic zone 410, in which the non-metallic atoms are mainly germanium. More preferably, zone 410 comprises, for example consists of, nickel germanide.

Next, the opening 600 is filled with an electrical conductor 700. The conductor 700 makes it possible to establish an electrical connection with the semiconductor region 110. For example, the conductor 700 can be covered and in contact with an electrical connection track between components. of an electronic chip.

An advantage of the method of FIGS. 5 to 7 and that the contact point with the semiconductor region 110, made up of regions 420 and 410, is self-aligned with the conductor 700. In an electronic chip comprising several contact points obtained by the method of FIGS. 5 to 7, this allows contacts to be made closer together than in a device in which the contacts are not thus self-aligned. It is therefore possible to increase, that is to say improve, the density of the components of the chip.

FIGS. 8 to 10 are sectional, partial and schematic views, representing steps of another embodiment of a method for forming a contact zone located on a semiconductor region 110 comprising germanium. The semiconductor region 110 is identical to that described in relation to FIG. 1. In particular, the semiconductor region 110 is preferably located on the front face side of a substrate 100.

At the step of FIG. 8, the semiconductor region 110 is covered with a multilayer 800 comprising, alternately, layers 802 of silicon and layers 804 of germanium. More precisely, the layers 802 have an atomic proportion of silicon greater than 70%. Preferably, the layers 802 are made of silicon, or of silicon–germanium having an atomic proportion of silicon greater than 70%. Layers 804 are germanium or consist primarily of germanium. Preferably, the layers 804 are made of germanium, or of silicon–germanium consisting mainly of germanium. By way of example, the thickness of the multilayer 800 is greater than 10 nm, preferably around 15 nm. Preferably, the layers 802 have the same thickness. Preferably, the layers 804 have the same thickness. More preferably, layers 802 and 804 all have the same thickness.

Preferably, the multilayer 800 is formed by epitaxy on the upper surface of the monocrystalline region 110. Each of the layers 802 and 804 then has a thickness less than a thickness threshold below which the layer remains monocrystalline. In practice, this threshold, or critical thickness, depends on the composition of the layers 802 and 804. By way of example, each of the layers 802 and 804 has a thickness of the order of, or less than, 2 nm. Thus, the multilayer 800 obtained is monocrystalline.

Steps similar to those of FIGS. 5 and 6 are then implemented, namely the successive formation of an insulating layer 510, of an opening 600 passing entirely through the insulating layer 510, of a metal layer 130, and of a possible protective layer 140. In practice, the opening 600 extends to a level located inside the multilayer 800. In the example shown, the bottom of the opening 600 is located in a layer 804A among the layers 804 consisting mainly of germanium. In another example, the bottom of the opening 600 stops inside one of the layers 802, or at an interface between one of the layers 802 and one of the layers 804. At least one of the layers 802 comprising at least 70% silicon is not reached by opening 600 and is therefore left intact. In the example represented, two of the layers 802 are not etched.

At the step of FIG. 9, the steps of FIGS. 2 and 3 have been implemented successively, that is to say the first heat treatment, and the removal of any protective layer 140 and the remains of the metallic layer 130. Preferably, the thickness of the metallic layer 130 deposited in the step of FIG. 8 is chosen sufficient so that each of the layers 802 and 804, as well as a part of the semiconductor region 110, reacts with the metal of the metallic layer 130. The reaction of each of the layers 802, 804 with the material of the metallic region 130A produces a respective zone 902, 904 under the opening 600. The parts of the structure located between the zones 902, 904 , and the rest of the multilayers 800, delimited in the figure by dotted lines 910, are not shown.

Preferably, the layer 904A (shown in dotted lines) is also removed, which results from the reaction of the layer 804A with the material of the metallic layer 130. This removal is preferably carried out with the same etching solution as that used to remove the remaining portions of metal region 130A. This is possible because the non-metallic atoms in the 904A region are mainly germanium atoms. This makes it possible to avoid keeping the zone 904A which would have been damaged by the etching solution. This makes accessible the upper face of zone 902 which was under and in contact with zone 904A before removal. Because more than 70%, or all, of the non-metallic atoms in area 902 are silicon, the etching solution leaves area 902 intact. Area 902 is therefore not damaged by the etch. Thus, the semiconductor region 110 is protected from the etching solution by at least one of the zones 902.

At the step of FIG. 10, the second heat treatment is carried out, as described in relation to FIG. 4. This transforms zones 902 and 904 respectively into zones 1002 and 1004. this example, of several superimposed intermetallic zones. The neighboring intermetallic zones are in contact with each other. From the semiconductor region 110, the contact successively comprises the zone 410 resulting from the reaction of a part of the semiconductor region 110 with the metallic layer 130; and :
- a zone 1002 having more than 70% of the non-metallic atoms made up of silicon; Where
- Several zones 1002 having more than 70% of the non-metallic atoms made up of silicon, separated by one or more zones 1004 having their non-metallic atoms mainly made up of germanium.

The rest of the cavity of opening 600 is then filled with an electrical conductor 700, preferably metallic. The zone 1002 located in the upper part of the contact socket is in electrical contact with the conductor 700. Since the upper zone 902 (FIG. 9) was not altered during the removal of the unreacted parts of the metallic layer 130, and because there is no intermetallic region from region 904A between region 1002 and electrical conductor 700, the strength and reliability of contact between the contact plug and conductor 700 is optimized.

In the preferred case of a single-crystal stack 800, the assembly of the contact point and the semiconductor region 110 is single-crystal. As a result, the electrical resistance of the contact plug is lower than that of a non-monocrystalline contact plug. This allows a further improvement in electrical resistance.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art based on the functional indications given above.

Claims (15)

A method of forming an electrical contact (400) with a semiconductor region (110) comprised primarily of germanium, comprising forming a first region (420) comprised of a first intermetallic material in which greater than 70% of the non-metal atoms are silicon. Electronic device comprising a semiconductor region (110) consisting mainly of germanium, and an electrical contact point (400) with the semiconductor region (110), the contact point (400) comprising a first zone (420) consisting of a first intermetallic material in which more than 70% of the non-metallic atoms are silicon. Method according to Claim 1 or device according to Claim 2, in which the contact point (400) comprises, between the first zone (420) and the semiconductor region (110), a second zone (410) made of a second material intermetallic in which the non-metallic atoms are mainly germanium. A method or device according to claim 3, wherein the metal atoms of each of the first and second intermetallic materials are predominantly nickel. A method or device according to claim 3 or 4, wherein each of the first and second intermetallic materials comprises platinum and/or cobalt. A method according to any of claims 1 and 3 to 5, or a device according to any of claims 2 to 5, wherein the first intermetallic material comprises germanium. Method according to any one of claims 1 and 3 to 6, in which the formation of the first zone (420) successively comprises:
a) the formation of at least one semiconductor layer (120; 120A; 802) covering the semiconductor region (110) and comprising at least 70% of silicon atoms;
b) forming a metallic region (130; 130A) on said at least one semiconductor layer (120; 120A; 802); and
c) reacting the metal region (130; 130A) with at least a portion of said at least one semiconductor layer (120; 120A; 802). A method according to claim 7, further comprising reacting the material of the metallic region (130; 130A) with that of the semiconductor region (110). Process according to claim 7 or 8, in which step c) comprises:
- a first heat treatment, preferably at a temperature below 300°C;
- a removal of parts of the metallic region (230) which have not reacted during the first heat treatment; and
- a second heat treatment, preferably at a temperature between 390°C and 420°C. Method according to any one of Claims 7 to 9, comprising, before step b), the formation of a protective layer (140), preferably of titanium nitride, on the metallic region (130, 130A). A method according to any of claims 7 to 10, comprising successively forming:
- an additional semiconductor layer (500) comprising at least 70% silicon atoms;
- an insulating layer (510) covering the additional semiconductor layer (500); and
- an opening (600) passing through the insulating layer (510) and the additional semiconductor layer (500),
said at least one semiconductor layer (120A) being formed in the opening (600) and forming, with the parts of the additional semiconductor layer (500) situated around the opening (600), a continuous layer. A method according to any one of claims 7 to 11, successively comprising forming:
- a multilayer (800) of first semiconductor layers (802) comprising at least 70% of silicon atoms alternated with second semiconductor layers (804) consisting mainly of germanium;
- an insulating layer (510) covering the multilayer (800); and
- an opening (600) passing through the insulating layer (510) and part of the multilayer (800),
said at least one semiconductor layer (802) consisting of the first layers (802) having been left intact under the opening (600). A method according to claim 12, wherein the multilayer (800) is single crystal. A method of manufacturing an electronic device, comprising the implementation of a method according to any one of claims 1 and 3 to 13. Photodiode comprising a device according to any one of claims 1 and 3 to 6 or a device obtained by a method according to claim 14.