FR3086475B1 - ELECTRONIC CIRCUIT WITH SYNCHRONIZED CLOCK DISTRIBUTION - Google Patents

ELECTRONIC CIRCUIT WITH SYNCHRONIZED CLOCK DISTRIBUTION Download PDF

Info

Publication number
FR3086475B1
FR3086475B1 FR1858643A FR1858643A FR3086475B1 FR 3086475 B1 FR3086475 B1 FR 3086475B1 FR 1858643 A FR1858643 A FR 1858643A FR 1858643 A FR1858643 A FR 1858643A FR 3086475 B1 FR3086475 B1 FR 3086475B1
Authority
FR
France
Prior art keywords
clk
terminal
acq2
clock signal
electronic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1858643A
Other languages
French (fr)
Other versions
FR3086475A1 (en
Inventor
Pascal Chatain
Stephane Brebion
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Moduleus SAS
Original Assignee
Moduleus SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Moduleus SAS filed Critical Moduleus SAS
Priority to FR1858643A priority Critical patent/FR3086475B1/en
Publication of FR3086475A1 publication Critical patent/FR3086475A1/en
Application granted granted Critical
Publication of FR3086475B1 publication Critical patent/FR3086475B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Abstract

La présente description concerne un circuit électronique comportant : - une première puce de circuits intégrés (ACQ2) comportant une première borne (CLK_IN) d'application d'un signal d'horloge d'entrée et une deuxième borne (CLK_OUT) de fourniture d'un signal d'horloge de sortie ; et - une deuxième puce de circuits intégrés (ACQ1) comportant une première borne (CLK_IN) d'application d'un signal d'horloge d'entrée reliée à la deuxième borne (CLK_OUT) de la première puce (ACQ2) par l'intermédiaire d'un conducteur de connexion (122), dans lequel la première puce (ACQ2) comporte un circuit de compensation de phase (207) configuré pour fournir sur sa deuxième borne (CLK_OUT) un signal d'horloge présentant, par rapport au signal d'horloge d'entrée appliqué sur sa première borne (CLK_IN), une avance de phase sensiblement égale au retard de phase introduit par le conducteur de connexion (122) entre les première (ACQ2) et deuxième (ACQ1) puces.The present description relates to an electronic circuit comprising: a first integrated circuit chip (ACQ2) comprising a first terminal (CLK_IN) for applying an input clock signal and a second terminal (CLK_OUT) for supplying an output clock signal; and - a second integrated circuit chip (ACQ1) comprising a first terminal (CLK_IN) for applying an input clock signal connected to the second terminal (CLK_OUT) of the first chip (ACQ2) via of a connection conductor (122), in which the first chip (ACQ2) comprises a phase compensation circuit (207) configured to supply on its second terminal (CLK_OUT) a clock signal having, with respect to the signal d input clock applied to its first terminal (CLK_IN), a phase advance substantially equal to the phase delay introduced by the connection conductor (122) between the first (ACQ2) and second (ACQ1) chips.

FR1858643A 2018-09-24 2018-09-24 ELECTRONIC CIRCUIT WITH SYNCHRONIZED CLOCK DISTRIBUTION Active FR3086475B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR1858643A FR3086475B1 (en) 2018-09-24 2018-09-24 ELECTRONIC CIRCUIT WITH SYNCHRONIZED CLOCK DISTRIBUTION

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1858643A FR3086475B1 (en) 2018-09-24 2018-09-24 ELECTRONIC CIRCUIT WITH SYNCHRONIZED CLOCK DISTRIBUTION

Publications (2)

Publication Number Publication Date
FR3086475A1 FR3086475A1 (en) 2020-03-27
FR3086475B1 true FR3086475B1 (en) 2021-05-21

Family

ID=65951628

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1858643A Active FR3086475B1 (en) 2018-09-24 2018-09-24 ELECTRONIC CIRCUIT WITH SYNCHRONIZED CLOCK DISTRIBUTION

Country Status (1)

Country Link
FR (1) FR3086475B1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4070255B2 (en) * 1996-08-13 2008-04-02 富士通株式会社 Semiconductor integrated circuit
US7120815B2 (en) * 2003-10-31 2006-10-10 Hewlett-Packard Development Company, L.P. Clock circuitry on plural integrated circuits
US7865756B2 (en) * 2007-03-12 2011-01-04 Mosaid Technologies Incorporated Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
FR3061616B1 (en) 2017-01-04 2020-10-02 Moduleus ULTRASONIC TRANSDUCER CONTROL CIRCUIT

Also Published As

Publication number Publication date
FR3086475A1 (en) 2020-03-27

Similar Documents

Publication Publication Date Title
TW200505140A (en) Low-to-high level shift circuit
TW200520123A (en) Method for mounting semiconductor chip and semiconductor chip-mounted board
EP2550655A1 (en) Enhancement of input/output for non source-synchronous interfaces
ATE543119T1 (en) MICROSCOPE CONFIGURATION PROVISION
DK1474749T3 (en) Supplementary command bus for a computer
FR3086475B1 (en) ELECTRONIC CIRCUIT WITH SYNCHRONIZED CLOCK DISTRIBUTION
TW344797B (en) Driver circuits for IC tester
WO2007091123B1 (en) System and method of determining the speed of digital application specific integrated circuits
EP0903755A3 (en) Ciruit and method to externally adjust internal circuit timing
US20010050856A1 (en) Semiconductor device, module including the semiconductor device, and system including the module
GB9809762D0 (en) Test chip circuit for on-chip timing characterization
TW200520378A (en) Impedance matching circuit and method
TW200513031A (en) Automatic correction device of clock duty cycle and method thereof
TW200636742A (en) Sense amplifier overdriving circuit and semiconductor device using the same
US20180076799A1 (en) Current-mode clock distribution
WO2007017057A3 (en) Circuit arrangement and method for converting an alternating voltage into a rectified voltage
US6810486B2 (en) Method and apparatus for de-skewing a clock using a first and second phase locked loop and a clock tree
TW200705851A (en) Light-receiving device, testing device, light-receiving method, testing method, test module and semiconductor chip
FR3088779B1 (en) Power supply circuit for switch control circuits
FR3079645B1 (en) ELECTRONIC DOCUMENT IN WHICH AN ELECTRICAL LINK BETWEEN A CHIP PORT AND AN EXTERNAL ELECTRICAL CONTACT RANGE IS ESTABLISHED VIA AN INLAY
DK1455391T3 (en) Power semiconductor module with follower component
JPS5920027A (en) Semiconductor device
TW200745573A (en) Method and circuits for sensing on-chip voltage in powerup mode
US9887693B2 (en) Clock selection circuit and power supply device equipped with the same
WO2007145653A3 (en) Semiconductor device and system and method of crystal sharing

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20200327

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6