FR3083885B1 - Circuit de generation de facteurs de rotation pour processeur ntt - Google Patents

Circuit de generation de facteurs de rotation pour processeur ntt Download PDF

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Publication number
FR3083885B1
FR3083885B1 FR1856340A FR1856340A FR3083885B1 FR 3083885 B1 FR3083885 B1 FR 3083885B1 FR 1856340 A FR1856340 A FR 1856340A FR 1856340 A FR1856340 A FR 1856340A FR 3083885 B1 FR3083885 B1 FR 3083885B1
Authority
FR
France
Prior art keywords
rotation factors
circuit
cache
bank
modular
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1856340A
Other languages
English (en)
Other versions
FR3083885A1 (fr
Inventor
Joel Cathebras
Alexandre Carbon
Renaud Sirdey
Nicolas Ventroux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1856340A priority Critical patent/FR3083885B1/fr
Priority to US17/259,065 priority patent/US20210334334A1/en
Priority to PCT/FR2019/051696 priority patent/WO2020012104A1/fr
Priority to EP19790625.8A priority patent/EP3803574A1/fr
Publication of FR3083885A1 publication Critical patent/FR3083885A1/fr
Application granted granted Critical
Publication of FR3083885B1 publication Critical patent/FR3083885B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/722—Modular multiplication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Computing Systems (AREA)
  • Discrete Mathematics (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Complex Calculations (AREA)

Abstract

La présente invention concerne un circuit de génération de facteurs de rotation (400) pour processeur NTT. Le circuit comprend un module gestionnaire de cache (410), un banc de multiplieurs modulaires (420) et un contrôleur central (430). Le module gestionnaire de cache comprend un contrôleur local (411) et une mémoire cache (412) dans laquelle sont stockés les opérandes pour le calcul des facteurs de rotation futurs. Le banc de multiplieurs modulaires comprend en entrée une matrice d'interconnexion distribuant les opérandes sur les entrées des multiplieurs modulaires. Le circuit peut être configuré pour minimiser la taille mémoire du cache et/ou réduire la latence de calcul de la séquence de facteurs de rotation. Le circuit de génération peut enfin comprendre plusieurs modules gestionnaires de calcul partageant un même banc de multiplieurs modulaires pour générer des séquences de facteurs de rotation sur plusieurs corps finis.
FR1856340A 2018-07-10 2018-07-10 Circuit de generation de facteurs de rotation pour processeur ntt Expired - Fee Related FR3083885B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1856340A FR3083885B1 (fr) 2018-07-10 2018-07-10 Circuit de generation de facteurs de rotation pour processeur ntt
US17/259,065 US20210334334A1 (en) 2018-07-10 2019-07-09 Twiddle factor generating circuit for an ntt processor
PCT/FR2019/051696 WO2020012104A1 (fr) 2018-07-10 2019-07-09 Circuit de génération de facteurs de rotation pour processeur ntt
EP19790625.8A EP3803574A1 (fr) 2018-07-10 2019-07-09 Circuit de génération de facteurs de rotation pour processeur ntt

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1856340 2018-07-10
FR1856340A FR3083885B1 (fr) 2018-07-10 2018-07-10 Circuit de generation de facteurs de rotation pour processeur ntt

Publications (2)

Publication Number Publication Date
FR3083885A1 FR3083885A1 (fr) 2020-01-17
FR3083885B1 true FR3083885B1 (fr) 2020-10-02

Family

ID=67262343

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1856340A Expired - Fee Related FR3083885B1 (fr) 2018-07-10 2018-07-10 Circuit de generation de facteurs de rotation pour processeur ntt

Country Status (4)

Country Link
US (1) US20210334334A1 (fr)
EP (1) EP3803574A1 (fr)
FR (1) FR3083885B1 (fr)
WO (1) WO2020012104A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT202000016393A1 (it) 2020-07-07 2022-01-07 St Microelectronics Srl Circuito di elaborazione di segnale digitale e corrispondente procedimento di funzionamento
CN112464296B (zh) * 2020-12-18 2022-09-23 合肥工业大学 一种用于同态加密技术的大整数乘法器硬件电路
CN116186473A (zh) * 2021-11-26 2023-05-30 华为技术有限公司 数据变换方法、装置及存储介质

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2842051B1 (fr) * 2002-04-30 2005-02-18 Oberthur Card Syst Sa Procede de cryptographie incluant le calcul d'une multiplication modulaire au sens de montgomery et entite electronique correspondante
US8527570B1 (en) * 2009-08-12 2013-09-03 Marvell International Ltd. Low cost and high speed architecture of montgomery multiplier
US20170329711A1 (en) * 2016-05-13 2017-11-16 Intel Corporation Interleaved cache controllers with shared metadata and related devices and systems
KR20230172043A (ko) * 2017-04-11 2023-12-21 더 가버닝 카운슬 오브 더 유니버시티 오브 토론토 동형 암호화에 의한 보안 계산 가속화를 위한 동형 처리 유닛

Also Published As

Publication number Publication date
FR3083885A1 (fr) 2020-01-17
US20210334334A1 (en) 2021-10-28
WO2020012104A1 (fr) 2020-01-16
EP3803574A1 (fr) 2021-04-14

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