EP3803574A1 - Circuit de génération de facteurs de rotation pour processeur ntt - Google Patents
Circuit de génération de facteurs de rotation pour processeur nttInfo
- Publication number
- EP3803574A1 EP3803574A1 EP19790625.8A EP19790625A EP3803574A1 EP 3803574 A1 EP3803574 A1 EP 3803574A1 EP 19790625 A EP19790625 A EP 19790625A EP 3803574 A1 EP3803574 A1 EP 3803574A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- cache memory
- bank
- modular
- rotation
- cache
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000015654 memory Effects 0.000 claims abstract description 84
- 239000011159 matrix material Substances 0.000 abstract description 4
- 230000009977 dual effect Effects 0.000 description 3
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/722—Modular multiplication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Definitions
- the present invention relates to the field of NTT (Number Theoretic Transform) processors. It finds particular application in cryptography on Euclidean network, in particular in homomorphic cryptography.
- NTT Numberer Theoretic Transform
- y is not necessarily a primitive root of GF (q), in other words its order is not necessarily equal to the order q - 1 of the multiplicative group of GF (q) but that the order N of y is necessarily a divisor of q - 1. If N and q are prime between them, there exists an inverse N 1 in the Galois field GF (q) and we can define the inverse integer transform or INTT (Inverse NTT) by: the inverses y nk existing to the extent that GF (q) is a field.
- the NTT transform is used in RNS (Residue Number System) arithmetic in the context of cryptography on a Euclidean network where it makes it possible to considerably simplify the multiplication of polynomials of high degrees and large coefficients.
- RNS Residue Number System
- the set ⁇ p 0 , ..., is called RNS base.
- the degrees of the polynomials are generally very high and the cryptoprocessors must be able to operate on a wide variety of finite bodies and unit roots, the required memory size is important.
- a second approach consists in calculating the rotation factors on the fly in order to supply them to the processor responsible for calculating the NTT.
- a general object of the present invention is to propose a circuit for generating rotation factors for an NTT processor which makes it possible to accelerate cryptographic calculations on a Euclidean network.
- a more specific object of the present invention is to propose a circuit for generating rotation factors which can adapt to the processing rate of an NTT processor per stream, while requiring only few local memory resources and / or not presenting only a low latency of computation.
- the present invention is defined by a circuit generating rotation factors on at least one finite body, for NTT processor by flow, said generating circuit being intended to generate at least a sequence of N rotation factors
- At least one cache manager module comprising a cache memory and a local controller controlling the writing and reading in the cache memory
- a bank of modular multipliers comprising a plurality of W modular multipliers operating in parallel, each modular multiplier performing a multiplication on said body of two operands originating from a word read from the cache memory;
- the cache memory can also include an address pointer pointing to the address where to read the value of U 0 for the next calculation cycle, the values of U V ..U W being read from the first part and the word U 0 U V ..U W formed by the concatenation of these values being supplied to the bank of modular multipliers for the next calculation cycle.
- the cache memory the central controller initializing the content of the cache memory with y 2 , y 2 ,., y 2 .
- y 2 the content of the cache memory
- the central controller initializing the content of the cache memory with y 2 , y 2 ,., y 2 .
- a word is read from the cache memory to prepare a cycle
- the word constituted by the results at the output of the bank of modular multipliers is stored following the content thus shifted.
- each cache manager module comprising a cache memory and a local controller controlling the writing and reading in the corresponding cache memory
- Each cache manager module can be provided at the input with a multiplexer controlled by the central controller, so as to transmit to the cache memory associated with the cache manager module, ie an initialization word, the G first rotation factors of the sequence corresponding, let W be the results of the modular multiplier bank.
- Fig. 1 schematically represents a dependency graph for the generation of the rotation factors
- Fig. 2 schematically represents a first example of overlapping of the graph of FIG. 1, corresponding to a first strategy for generating the rotation factors;
- FIG. 3 schematically represents a second example of overlapping of the graph of FIG. 1, corresponding to a second strategy for generating the rotation factors;
- Fig. 4 schematically represents the general architecture of a circuit for generating rotation factors according to a first embodiment of the invention
- Fig. 5 schematically represents the general architecture of a bench of modular multipliers for the generation circuit of FIG. 4;
- Fig. 6A schematically represents a first example of a bank of modular multipliers
- Fig. 6B illustrates the strategy for generating the rotation factors using the modular multiplier bank of FIG. 6A
- Fig. 6C schematically represents the scheduling of the calculations in the circuit for generating the rotation factors when the bank of modular multipliers is that of FIG. 6A;
- Fig. 7A schematically represents a second example of a bench of modular multipliers
- Fig. 7B illustrates the strategy for generating the rotation factors using the modular multiplier bank of FIG. 7A
- Fig. 7C schematically represents the scheduling of the calculations in the circuit for generating the rotation factors when the bank of modular multipliers is that of FIG. 7A;
- Fig. 8 schematically represents the general architecture of a circuit for generating rotation factors according to a second embodiment of the invention.
- Fig. 9 schematically represents the scheduling of the calculations in the circuit for generating the rotation factors of FIG. 8.
- the generation of the rotation factors can be represented using an oriented graph, called the dependency graph, in which each node represents a power y h , a power y being associated with as many nodes as there are ways to calculate it. from the previous nodes.
- Each node of the graph, except the one representing the root y, is supposed to have an incoming degree (number of arcs ending at this node) less than or equal to 2, in other words each rotation factor y is generated from at most 2 previous factors only.
- Fig. 1 illustrates the dependency graph for the generation of the first six elements of the series ⁇ y
- n 0, ..., N -l ⁇ .
- the arcs identify the parents of each node.
- y 6 can be calculated in six different ways depending on the parents chosen.
- the weight associated with each arc is that of the kinship factor.
- a node can be the end of two arcs of weight 1 (for example y 6 is calculated as the product y i y 5 or y 2 y A from two distinct parent nodes) or of a single arc of weight 2 (for example y 6 is calculated as the product y 3 y 3 from a single parent node).
- the dependency graph can be browsed in order to minimize the local memory requirements or the computation latency for the generation of the rotation factors.
- Fig. 2 shows a first example of an overlap of the graph in FIG. 1, aimed at minimizing the memory resource requirements.
- Fig. 3 represents a second example of an overlap of the graph of FIG. 1, aimed at minimizing the computing latency.
- a rotation factor is generated as soon as the rotation factors of the parent nodes are available.
- the strategy for generating the rotation factors corresponding to this graph overlap can be represented by the following recurrence relation:
- the rotation factor generation circuit generates the series y h
- the NTT processor performs a radix operation (similar to a radix operation in an FFT) relating to W input data.
- FIG. 4 schematically represents the general architecture of a circuit for generating rotation factors according to a first embodiment of the invention.
- the generation circuit 400 essentially comprises a cache manager module, 410, a bench of modular multipliers, 420, and a central controller, 430.
- the cache manager module has a local controller, 411, a cache memory 412, an output register 415 to supply W rotation factors at each cycle as well as an intermediate output register 417 to supply, at the start of each cycle of operands from the cache memory on the bench of modular multipliers.
- the cache manager module has the function of time the calculations of the series of rotation factors according to the recovery strategy of the dependency graph used.
- the modular multiplier bank receives operands from the cache manager module at each cycle, namely powers y / stored in the cache memory, and deduces therefrom the rotation factors to be supplied for the current cycle.
- the rotation factors thus calculated are supplied to the output register 415 and stored in the cache memory. More precisely, the results at the output of the modular multipliers are supplied to an intermediate input register 407 before being transmitted to the output register 415 and stored in the cache memory 412.
- the G initial rotation factors y / 1 , ..., y / G are supplied to the cache manager module 410 via an input register 405.
- the outputs of the input register and of the intermediate input register are multiplexed by the multiplexer 409.
- This multiplexer controlled by the central controller 430, transmits the initial rotation factors to the input of the cache manager module during the initialization of a series of T cycles, then the rotation factors calculated by the bank of modular multipliers towards the input of the cache manager module at the start of each of the following T - 1 cycles of the series.
- the central controller 430 generates a GenCtrl set of control signals consisting of the new _ set, compute and new _ data signals which control the local controller of the cache manager module.
- the first control signal, new _ set is used to initialize the calculation manager every T cycles and in particular to reset the internal counters of the local controller. It also instructs the input multiplexer 409 to transmit to the cache manager module, the initial rotation factors ⁇ y i , ..., y ° J received on the input register 405.
- the second control signal computes, commands the cache manager module to carry out a calculation cycle, that is to say to read the operands in the cache memory and supply them to the bank of modular multipliers 420.
- the third control signal, new _ data indicates the local controller that he must take into account the new rotation factors calculated by the modular multiplier bank.
- the local controller informs the central controller when it is ready to perform a new calculation using data availability information. More specifically, this availability information takes a high logical value when the cache 412 contains the rotation factors making it possible to calculate the following elements of the series and the central controller has not yet ordered these calculations by means of the computed signal.
- the local controller comprises a first counter recording the number of rotation factors already generated, a second counter recording the number of rotation factors stored in the cache memory and a third counter recording the number of calculation cycles requested by the central controller from the last initialization (i.e. from the start of the series).
- the local controller comprises a combinational logic circuit receiving the control signals from the central controller and supplying the control signals from the aforementioned counters, the availability information, the control signals from the cache memory as well as from the output register.
- the output register control signal makes it possible to supply the W last rotation factors generated on the output bus.
- the central controller is essentially composed of a combinational logic circuit and a shift register.
- the depth of the shift register is determined according to the latency of the bank of modular multipliers (to perform the calculations) as well as the latency of the cache manager module (to update the output register and its intermediate output register) .
- the shift register advances at each clock cycle.
- the central controller receives as input a new _ input signal indicating that a new set of initial rotation factors y L is available on the input bus for a new series of rotation factor calculations ⁇ y '
- n 0, ..., / V -lJ where y 'is a new root of the unit in ⁇ r .
- the central controller also receives data _ available availability information from the cache manager module. From the new _input and data _ available signals the combinatorial logic circuit of the central controller generates the new _ set, compute and new _ data control signals for the next calculation cycle.
- the combinational logic circuit updates the entry of the shift register at the start of each calculation cycle. At the output of the shift register, in other words after taking into account the respective latencies of the bank of modular multipliers, a valid signal is generated, indicating that a set of W rotation factors is available on the output bus.
- Fig. 5 schematically represents the general architecture of a bench of modular multipliers for the generation circuit of FIG. 4.
- It includes an interconnection matrix, 510, intended to receive the operands from the cache memory and to distribute them on the inputs of W modular multipliers operating in parallel, 520, designated by each modular multiplier MM w performing a modulo p multiplication of its two input operands to provide the result R w .
- Fig. 6A schematically represents a first example of a bench of modular multipliers.
- This implementation example corresponds to a strategy for minimizing the size of the cache memory of the cache manager module.
- the interconnection matrix receives W + 1 operands and distributes them over the 2 W inputs of the modular multipliers.
- R 1 U 0 U 2 mod p ...
- R w - 1 U, IJ, V mod p (7)
- the outputs of the modular multiplier bank are represented in 650 to 657, or more precisely the data at the output of the multiplexer 409 (insofar as 650 corresponds to the initialization state), for 8 successive calculation cycles.
- the values appearing in the boxes in broken lines are those which are stored in a second part of the cache memory as explained below.
- Fig. 6C schematically represents the scheduling of the calculations in the circuit for generating the rotation factors when the bank of modular multipliers is implemented as in FIG. 6A.
- the operands U 0 , ..., U 4 are shown in 661 at the input of the battery of modular multipliers; in 662 and 663 a first part and a second part of the cache memory, denoted AGRS and AGR0; in 665 the results R 0 , ..., R 3 at the output of the bank of modular multipliers.
- AGRS The size of AGRS is equal to W, that of AGR0 is equal to LatMM + 1. (it was assumed in the illustrated example that the modular multiplier bank had a LatMM latency of 3 clock cycles).
- AGRS The memory locations of AGRS are denoted C 0 , ..., C 3 , those of AGR0 are denoted B 0 , ..., B 3 .
- R 0 , ..., R 3 and in AGR0 in B 0 , ..., B 3 rotation factors, called reserve , defined as the LatMM + 1 first rotation factors y / of the series where i is a multiple of W.
- reserve rotation factors
- the operands U V ..., U 4 are read from the memory locations C 0 , ..., C 3 of AGRS and the operand U 0 is read from AGRO at the address given by the index Ind in 664. This index is generated by the local controller of the cache manager module.
- Fig. 7A schematically represents a second example of a bench of modular multipliers. This implementation example corresponds to the earliest generation of the rotation factors.
- the interconnection matrix receives here— +1 operands and distributes them over the 2 W
- the bank of modular multipliers performs the following operations:
- Fig. 7B illustrates the strategy for generating the rotation factors using the modular multiplier bank of FIG. 7A.
- Fig. 7C schematically represents the scheduling of the calculations in the circuit for generating the rotation factors when the bank of modular multipliers is implemented as in FIG. 7A.
- the calculation of the series of rotation factors ⁇ 1 , ..., ⁇ 32 ⁇ begins as before with the reception of the initial values y i,. ., y 4 .
- the initial values ⁇ 2 , ..., ⁇ 4 J are stored (at time t 0 ) in cache memory at the locations C 0 , ..., C 2 .
- the value y 4 remains stored, at location C 0 .
- the results appearing at the output of the modular multiplier bank at the end of LatMM (at time i 5 ) are then .
- the results R 0 , ..., R 3 are stored following C 0 at the locations C V .., C 4 for the preparation of the following calculations.
- the results R O , ..., R 3 are stored following C 0 at the locations C V .., C 4 for the preparation of the following calculations.
- the stored values are supplied to the battery of modular multipliers with
- the size of the cache in the second example is -. Indeed, at
- waiting times are present in the supply of the battery of modular multipliers, due to the latency LatMM and dependency relationships to respect in the dependency graph.
- the result a jerky generation of rotation factors, at least the first elements of the series.
- Fig. 8 schematically represents the general architecture of a circuit for generating rotation factors according to a second embodiment of the invention.
- the circuit for generating the rotation factors here comprises a plurality L of cache manager modules 810O, ..., 810L-I, each having the structure of the cache manager module 410.
- Each of these modules is associated with a finite body Z and has its local controller as well as its cache memory. At the output of each of these modules, there is an output bus and an intermediate output bus.
- the output buses of the various cache management modules are multiplexed by a first output multiplexer 841 controlled by the central controller by means of a SEL _ output command.
- the intermediate output buses of the various cache management modules are multiplexed by a second output multiplexer 842, controlled by the central controller by means of a SEL _ MMS command.
- the circuit for generating rotation factors comprises a bank of modular multipliers, 820, and a central controller, 830.
- the modular multiplier bank 820 is supplied with data via a common register, 850, at the output of the second output multiplexer. It also receives from the central controller a modulo t signal indicating to the modular multipliers in which body Z the multiplications must be carried out.
- the rotation factors calculated by the modular multiplier bank are provided via the intermediate input register 807.
- the respective outputs of the input register and of the intermediate input register are each distributed to all the calculation manager modules.
- Each cache manager module, 81 (3 ⁇ 4, has as input an associated multiplexer, 809 ; controlled by the central controller 830.
- the central controller can indicate to one of the calculation manager modules 810 ⁇ , to import the factors of initial rotation or rotation factors calculated by the bank of modular multipliers.
- the central controller provides the control signals for the first and second output multiplexers 841, 843.
- the central controller indicates this by means of the signal valid and precise by means of the signal num to which body Z this game belongs.
- Fig. 9 schematically represents the scheduling of the calculations in the circuit for generating the rotation factors of FIG. 8.
- the sets of initial values have been represented; in 920, the operands U 0 , U V U 2 at the input of the battery of modular multipliers; in 930 the results at the output of the modular multiplier bank and in 940 the output of the first output multiplexer.
- the shaded boxes correspond to the insertion of a new set of initial values.
- the elements of the different series are output as soon as they are generated.
- the digital signal distinguishes them.
- this signal could be used by an NTT processor by flow to separate NTTs on different bodies.
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- Software Systems (AREA)
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Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1856340A FR3083885B1 (fr) | 2018-07-10 | 2018-07-10 | Circuit de generation de facteurs de rotation pour processeur ntt |
PCT/FR2019/051696 WO2020012104A1 (fr) | 2018-07-10 | 2019-07-09 | Circuit de génération de facteurs de rotation pour processeur ntt |
Publications (1)
Publication Number | Publication Date |
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EP3803574A1 true EP3803574A1 (fr) | 2021-04-14 |
Family
ID=67262343
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19790625.8A Withdrawn EP3803574A1 (fr) | 2018-07-10 | 2019-07-09 | Circuit de génération de facteurs de rotation pour processeur ntt |
Country Status (4)
Country | Link |
---|---|
US (1) | US20210334334A1 (fr) |
EP (1) | EP3803574A1 (fr) |
FR (1) | FR3083885B1 (fr) |
WO (1) | WO2020012104A1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT202000016393A1 (it) * | 2020-07-07 | 2022-01-07 | St Microelectronics Srl | Circuito di elaborazione di segnale digitale e corrispondente procedimento di funzionamento |
CN112464296B (zh) * | 2020-12-18 | 2022-09-23 | 合肥工业大学 | 一种用于同态加密技术的大整数乘法器硬件电路 |
CN116186473A (zh) * | 2021-11-26 | 2023-05-30 | 华为技术有限公司 | 数据变换方法、装置及存储介质 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2842051B1 (fr) * | 2002-04-30 | 2005-02-18 | Oberthur Card Syst Sa | Procede de cryptographie incluant le calcul d'une multiplication modulaire au sens de montgomery et entite electronique correspondante |
US8527570B1 (en) * | 2009-08-12 | 2013-09-03 | Marvell International Ltd. | Low cost and high speed architecture of montgomery multiplier |
US20170329711A1 (en) * | 2016-05-13 | 2017-11-16 | Intel Corporation | Interleaved cache controllers with shared metadata and related devices and systems |
CA3034597C (fr) * | 2017-04-11 | 2021-10-12 | The Governing Council Of The University Of Toronto | Un module de traitement homomorphe destine a accelerer les calculs securises de chiffrement homomorphe |
-
2018
- 2018-07-10 FR FR1856340A patent/FR3083885B1/fr not_active Expired - Fee Related
-
2019
- 2019-07-09 WO PCT/FR2019/051696 patent/WO2020012104A1/fr unknown
- 2019-07-09 EP EP19790625.8A patent/EP3803574A1/fr not_active Withdrawn
- 2019-07-09 US US17/259,065 patent/US20210334334A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20210334334A1 (en) | 2021-10-28 |
FR3083885A1 (fr) | 2020-01-17 |
WO2020012104A1 (fr) | 2020-01-16 |
FR3083885B1 (fr) | 2020-10-02 |
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