FR3077892B1 - Système et procédé d'enregistrement d'une transaction associée à une mémoire non volatile orientée page - Google Patents

Système et procédé d'enregistrement d'une transaction associée à une mémoire non volatile orientée page Download PDF

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Publication number
FR3077892B1
FR3077892B1 FR1901332A FR1901332A FR3077892B1 FR 3077892 B1 FR3077892 B1 FR 3077892B1 FR 1901332 A FR1901332 A FR 1901332A FR 1901332 A FR1901332 A FR 1901332A FR 3077892 B1 FR3077892 B1 FR 3077892B1
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France
Prior art keywords
page
transaction
recording
oriented memory
volatile
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Active
Application number
FR1901332A
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English (en)
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FR3077892A1 (fr
Inventor
Mrityunjay Kumar
Mohammad Ovais Siddiqui
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Idemia
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Idemia
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Publication of FR3077892A1 publication Critical patent/FR3077892A1/fr
Application granted granted Critical
Publication of FR3077892B1 publication Critical patent/FR3077892B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/466Transaction processing
    • G06F9/467Transactional memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/466Transaction processing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1402Saving, restoring, recovering or retrying
    • G06F11/1446Point-in-time backing up or restoration of persistent data
    • G06F11/1448Management of the data involved in backup or backup restore
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1402Saving, restoring, recovering or retrying
    • G06F11/1446Point-in-time backing up or restoration of persistent data
    • G06F11/1458Management of the backup or restore process
    • G06F11/1466Management of the backup or restore process to make the backup process non-disruptive
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1402Saving, restoring, recovering or retrying
    • G06F11/1446Point-in-time backing up or restoration of persistent data
    • G06F11/1458Management of the backup or restore process
    • G06F11/1469Backup restoration techniques
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1009Address translation using page tables, e.g. page table structures
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/54Interprogram communication
    • G06F9/544Buffers; Shared memory; Pipes
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • G06F2212/1024Latency reduction
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1041Resource optimization
    • G06F2212/1044Space efficiency improvement
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7203Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Système et procédé d'enregistrement d'une transaction associée à une mémoire non volatile orientée page. Un procédé d'enregistrement des transactions associées à une mémoire non volatile orientée page est décrit. Le procédé comprend l'identification des pages nécessitant une ou plusieurs mise(s) à jour pour la mise en œuvre d'une transaction définie. De plus, le procédé comprend la copie de la page dans un tampon non volatil. Le procédé comprend en outre la mise à jour de la page identifiée avec le contenu de la transaction. La transaction est validée si la page est mise à jour sans interruption sinon toute la transaction est annulée. Figure pour l’abrégé : Fig. 3
FR1901332A 2018-02-15 2019-02-11 Système et procédé d'enregistrement d'une transaction associée à une mémoire non volatile orientée page Active FR3077892B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IN201811005799 2018-02-15
IN201811005799 2018-02-15

Publications (2)

Publication Number Publication Date
FR3077892A1 FR3077892A1 (fr) 2019-08-16
FR3077892B1 true FR3077892B1 (fr) 2023-12-22

Family

ID=67540900

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1901332A Active FR3077892B1 (fr) 2018-02-15 2019-02-11 Système et procédé d'enregistrement d'une transaction associée à une mémoire non volatile orientée page

Country Status (2)

Country Link
US (1) US11150940B2 (fr)
FR (1) FR3077892B1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7620660B2 (en) * 2005-06-30 2009-11-17 Microsoft Corporation Pre-image logging for database recovery
US9207876B2 (en) * 2007-04-19 2015-12-08 Microsoft Technology Licensing, Llc Remove-on-delete technologies for solid state drive optimization
EP2270662A1 (fr) * 2009-06-29 2011-01-05 Thomson Licensing Procédé et appareil pour traiter des erreurs d'écriture lors de l'entrée de données d'information dans des dispositifs à mémoire flash
US9519591B2 (en) * 2013-06-22 2016-12-13 Microsoft Technology Licensing, Llc Latch-free, log-structured storage for multiple access methods

Also Published As

Publication number Publication date
US11150940B2 (en) 2021-10-19
US20190250945A1 (en) 2019-08-15
FR3077892A1 (fr) 2019-08-16

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