FR3072799B1 - Combinaison d'etats de multiples fils d'execution dans un processeur a fils d'execution multiples - Google Patents
Combinaison d'etats de multiples fils d'execution dans un processeur a fils d'execution multiples Download PDFInfo
- Publication number
- FR3072799B1 FR3072799B1 FR1859635A FR1859635A FR3072799B1 FR 3072799 B1 FR3072799 B1 FR 3072799B1 FR 1859635 A FR1859635 A FR 1859635A FR 1859635 A FR1859635 A FR 1859635A FR 3072799 B1 FR3072799 B1 FR 3072799B1
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- Prior art keywords
- multiple threaded
- states
- processor
- combining
- combining multiple
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
- G06F15/17325—Synchronisation; Hardware support therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/3009—Thread control instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/461—Saving or restoring of program or task context
- G06F9/462—Saving or restoring of program or task context with multiple register sets
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
- G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/522—Barrier synchronisation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Multimedia (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1717300.6A GB2569098B (en) | 2017-10-20 | 2017-10-20 | Combining states of multiple threads in a multi-threaded processor |
GB17173006 | 2017-10-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3072799A1 FR3072799A1 (fr) | 2019-04-26 |
FR3072799B1 true FR3072799B1 (fr) | 2022-06-03 |
Family
ID=60481649
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1859635A Active FR3072799B1 (fr) | 2017-10-20 | 2018-10-18 | Combinaison d'etats de multiples fils d'execution dans un processeur a fils d'execution multiples |
Country Status (10)
Country | Link |
---|---|
US (2) | US10452396B2 (fr) |
JP (1) | JP6698784B2 (fr) |
KR (1) | KR102253628B1 (fr) |
CN (1) | CN110121702B (fr) |
CA (1) | CA3021407C (fr) |
DE (1) | DE102018126003A1 (fr) |
FR (1) | FR3072799B1 (fr) |
GB (1) | GB2569098B (fr) |
TW (1) | TWI703496B (fr) |
WO (1) | WO2019076713A1 (fr) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10474458B2 (en) | 2017-04-28 | 2019-11-12 | Intel Corporation | Instructions and logic to perform floating-point and integer operations for machine learning |
GB2569098B (en) | 2017-10-20 | 2020-01-08 | Graphcore Ltd | Combining states of multiple threads in a multi-threaded processor |
US20190319933A1 (en) * | 2018-04-12 | 2019-10-17 | Alibaba Group Holding Limited | Cooperative tls acceleration |
US11062680B2 (en) * | 2018-12-20 | 2021-07-13 | Advanced Micro Devices, Inc. | Raster order view |
GB2580165B (en) | 2018-12-21 | 2021-02-24 | Graphcore Ltd | Data exchange in a computer with predetermined delay |
US11934342B2 (en) | 2019-03-15 | 2024-03-19 | Intel Corporation | Assistance for hardware prefetch in cache access |
CN113366454A (zh) | 2019-03-15 | 2021-09-07 | 英特尔公司 | 用于图形操作的多片架构 |
CN112534405A (zh) | 2019-03-15 | 2021-03-19 | 英特尔公司 | 用于脉动阵列上的块稀疏操作的架构 |
US11126439B2 (en) * | 2019-11-15 | 2021-09-21 | Apple Inc. | SIMD operand permutation with selection from among multiple registers |
GB2596872B (en) * | 2020-07-10 | 2022-12-14 | Graphcore Ltd | Handling injected instructions in a processor |
GB202010839D0 (en) * | 2020-07-14 | 2020-08-26 | Graphcore Ltd | Variable allocation |
GB2608180B (en) * | 2021-06-25 | 2024-06-26 | Graphcore Ltd | Control of data send from a multi-processor device |
US20230315460A1 (en) * | 2022-04-02 | 2023-10-05 | Intel Corporation | Synchronous microthreading |
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JPH06139220A (ja) * | 1992-10-30 | 1994-05-20 | Hitachi Ltd | ニューロコンピュータ |
DE69429204T2 (de) * | 1993-03-26 | 2002-07-25 | Cabletron Systems Inc | Ablaufssteuerungsverfahren und -gerät für ein Kommunikationsnetzwerk |
GB2296534B (en) | 1993-07-20 | 1996-12-04 | Graco Inc | A two-stage air valve actuator for a double-diaphragm pump |
JP3169779B2 (ja) * | 1994-12-19 | 2001-05-28 | 日本電気株式会社 | マルチスレッドプロセッサ |
WO2000070446A2 (fr) * | 1999-05-13 | 2000-11-23 | Arc International U.S. Holdings Inc. | Procede et appareil d'encodage de registre libre dans un processeur pipeline |
US20030126416A1 (en) * | 2001-12-31 | 2003-07-03 | Marr Deborah T. | Suspending execution of a thread in a multi-threaded processor |
CN1842770A (zh) * | 2003-08-28 | 2006-10-04 | 美普思科技有限公司 | 一种在处理器中挂起和释放执行过程中计算线程的整体机制 |
US20060136919A1 (en) * | 2004-12-17 | 2006-06-22 | Sun Microsystems, Inc. | System and method for controlling thread suspension in a multithreaded processor |
US7810083B2 (en) * | 2004-12-30 | 2010-10-05 | Intel Corporation | Mechanism to emulate user-level multithreading on an OS-sequestered sequencer |
US20060146864A1 (en) * | 2004-12-30 | 2006-07-06 | Rosenbluth Mark B | Flexible use of compute allocation in a multi-threaded compute engines |
KR100728899B1 (ko) * | 2005-10-27 | 2007-06-15 | 한국과학기술원 | 복수의 레지스터 집합과 하드웨어 작업 관리자를 가진고성능 멀티쓰레드 임베디드 프로세서 |
US8194690B1 (en) * | 2006-05-24 | 2012-06-05 | Tilera Corporation | Packet processing in a parallel processing environment |
US8868888B2 (en) * | 2007-09-06 | 2014-10-21 | Qualcomm Incorporated | System and method of executing instructions in a multi-stage data processing pipeline |
US20090171379A1 (en) * | 2007-12-27 | 2009-07-02 | Ethicon Endo-Surgery, Inc. | Fluid logic for regulating restriction devices |
DE102008020782B4 (de) * | 2008-04-25 | 2010-08-12 | Fujitsu Siemens Computers Gmbh | Verfahren zur parallelen Verarbeitung von Programmen sowie zur Durchführung des Verfahrens geeigneter Prozessor |
JP5379122B2 (ja) * | 2008-06-19 | 2013-12-25 | パナソニック株式会社 | マルチプロセッサ |
JP2010176403A (ja) * | 2009-01-29 | 2010-08-12 | Toyota Motor Corp | マルチスレッドプロセッサ装置 |
US8423750B2 (en) * | 2010-05-12 | 2013-04-16 | International Business Machines Corporation | Hardware assist thread for increasing code parallelism |
US8713290B2 (en) * | 2010-09-20 | 2014-04-29 | International Business Machines Corporation | Scaleable status tracking of multiple assist hardware threads |
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CN103530089B (zh) * | 2012-08-31 | 2018-06-15 | 威盛电子股份有限公司 | 微处理器及其操作方法 |
TW201423402A (zh) * | 2012-12-12 | 2014-06-16 | Paneve Llc | 通用目的數位資料處理器、系統及方法 |
JP5981352B2 (ja) * | 2013-01-04 | 2016-08-31 | 日本電信電話株式会社 | 半導体装置の製造方法 |
US9575802B2 (en) * | 2014-10-28 | 2017-02-21 | International Business Machines Corporation | Controlling execution of threads in a multi-threaded processor |
JP6007430B2 (ja) * | 2015-05-20 | 2016-10-12 | 大澤 昇平 | 機械学習モデル設計支援装置、機械学習モデル設計支援方法、機械学習モデル設計支援装置用プログラム |
US9645937B2 (en) * | 2015-08-28 | 2017-05-09 | International Business Machines Corporation | Expedited servicing of store operations in a data processing system |
US10832120B2 (en) * | 2015-12-11 | 2020-11-10 | Baidu Usa Llc | Systems and methods for a multi-core optimized recurrent neural network |
GB2569098B (en) | 2017-10-20 | 2020-01-08 | Graphcore Ltd | Combining states of multiple threads in a multi-threaded processor |
GB2569269B (en) * | 2017-10-20 | 2020-07-15 | Graphcore Ltd | Synchronization in a multi-tile processing arrangement |
GB2569273B (en) * | 2017-10-20 | 2020-01-01 | Graphcore Ltd | Synchronization in a multi-tile processing arrangement |
GB2569274B (en) * | 2017-10-20 | 2020-07-15 | Graphcore Ltd | Synchronization amongst processor tiles |
GB2569271B (en) * | 2017-10-20 | 2020-05-13 | Graphcore Ltd | Synchronization with a host processor |
-
2017
- 2017-10-20 GB GB1717300.6A patent/GB2569098B/en active Active
-
2018
- 2018-02-01 US US15/885,955 patent/US10452396B2/en active Active
- 2018-10-11 WO PCT/EP2018/077673 patent/WO2019076713A1/fr active Application Filing
- 2018-10-11 CN CN201880004212.3A patent/CN110121702B/zh active Active
- 2018-10-17 TW TW107136460A patent/TWI703496B/zh active
- 2018-10-18 FR FR1859635A patent/FR3072799B1/fr active Active
- 2018-10-19 DE DE102018126003.2A patent/DE102018126003A1/de active Pending
- 2018-10-19 JP JP2018197225A patent/JP6698784B2/ja active Active
- 2018-10-19 CA CA3021407A patent/CA3021407C/fr active Active
- 2018-10-22 KR KR1020180126034A patent/KR102253628B1/ko active IP Right Grant
-
2019
- 2019-08-01 US US16/529,122 patent/US11113060B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20190354370A1 (en) | 2019-11-21 |
WO2019076713A1 (fr) | 2019-04-25 |
TWI703496B (zh) | 2020-09-01 |
DE102018126003A1 (de) | 2019-04-25 |
US20190121638A1 (en) | 2019-04-25 |
CN110121702B (zh) | 2023-07-21 |
CA3021407A1 (fr) | 2019-04-20 |
CN110121702A (zh) | 2019-08-13 |
GB201717300D0 (en) | 2017-12-06 |
TW201923562A (zh) | 2019-06-16 |
GB2569098A (en) | 2019-06-12 |
JP2019079527A (ja) | 2019-05-23 |
KR102253628B1 (ko) | 2021-05-18 |
US11113060B2 (en) | 2021-09-07 |
CA3021407C (fr) | 2020-12-29 |
GB2569098B (en) | 2020-01-08 |
KR20190044569A (ko) | 2019-04-30 |
JP6698784B2 (ja) | 2020-05-27 |
US10452396B2 (en) | 2019-10-22 |
FR3072799A1 (fr) | 2019-04-26 |
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