FR3068798B1 - Procede de generation d'un agencement de circuit 3d a partir d'un agencement de circuit 2d - Google Patents

Procede de generation d'un agencement de circuit 3d a partir d'un agencement de circuit 2d Download PDF

Info

Publication number
FR3068798B1
FR3068798B1 FR1756352A FR1756352A FR3068798B1 FR 3068798 B1 FR3068798 B1 FR 3068798B1 FR 1756352 A FR1756352 A FR 1756352A FR 1756352 A FR1756352 A FR 1756352A FR 3068798 B1 FR3068798 B1 FR 3068798B1
Authority
FR
France
Prior art keywords
circuit
circuit layout
row
generation
layout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1756352A
Other languages
English (en)
Other versions
FR3068798A1 (fr
Inventor
Guillaume Berhault
Olivier Billoint
Sebastien Thuries
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1756352A priority Critical patent/FR3068798B1/fr
Priority to US16/027,545 priority patent/US10740528B2/en
Priority to EP18181802.2A priority patent/EP3425541B1/fr
Publication of FR3068798A1 publication Critical patent/FR3068798A1/fr
Application granted granted Critical
Publication of FR3068798B1 publication Critical patent/FR3068798B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé de génération, par un dispositif informatique, d'un agencement de circuit 3D sur la base d'un agencement de circuit 2D, le procédé comprenant : affecter des cellules d'un premier et d'un deuxième groupe de cellules de circuit de l'agencement de circuit 2D à des premier et deuxième niveaux de l'agencement de circuit 3D, l'affectation de chaque cellule de circuit des premier et deuxième groupes étant réalisée en sélectionnant, entre au moins une première rangée d'un premier niveau et au moins une deuxième rangée d'un deuxième niveau de l'agencement de circuit 3D, la rangée ayant l'espace disponible le plus grand, et en affectant la cellule de circuit à la rangée sélectionnée ; et transmettre l'agencement de circuit 3D à une usine de fabrication pour sa fabrication.
FR1756352A 2017-07-05 2017-07-05 Procede de generation d'un agencement de circuit 3d a partir d'un agencement de circuit 2d Expired - Fee Related FR3068798B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1756352A FR3068798B1 (fr) 2017-07-05 2017-07-05 Procede de generation d'un agencement de circuit 3d a partir d'un agencement de circuit 2d
US16/027,545 US10740528B2 (en) 2017-07-05 2018-07-05 Method of generating a 3D circuit layout from a 2D circuit layout
EP18181802.2A EP3425541B1 (fr) 2017-07-05 2018-07-05 Procédé de génération d'une topologie de circuit 3d à partir d'une topologie de circuit 2d

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1756352 2017-07-05
FR1756352A FR3068798B1 (fr) 2017-07-05 2017-07-05 Procede de generation d'un agencement de circuit 3d a partir d'un agencement de circuit 2d

Publications (2)

Publication Number Publication Date
FR3068798A1 FR3068798A1 (fr) 2019-01-11
FR3068798B1 true FR3068798B1 (fr) 2021-12-31

Family

ID=60302189

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1756352A Expired - Fee Related FR3068798B1 (fr) 2017-07-05 2017-07-05 Procede de generation d'un agencement de circuit 3d a partir d'un agencement de circuit 2d

Country Status (3)

Country Link
US (1) US10740528B2 (fr)
EP (1) EP3425541B1 (fr)
FR (1) FR3068798B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10678987B2 (en) * 2017-10-25 2020-06-09 Taiwan Semiconductor Manufacturing Company Ltd. Cell layout method and system for creating stacked 3D integrated circuit having two tiers
CN111710644B (zh) * 2020-05-20 2022-01-04 西南科技大学 一种基于硅通孔的三维集成电路布局方法
CN116976269B (zh) * 2023-08-01 2024-09-03 北京华大九天科技股份有限公司 填充方法及装置、计算装置和存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6370673B1 (en) * 1999-03-22 2002-04-09 Synopsys, Inc. Method and system for high speed detailed placement of cells within an integrated circuit design
US7526739B2 (en) * 2005-07-26 2009-04-28 R3 Logic, Inc. Methods and systems for computer aided design of 3D integrated circuits
EP2469597A3 (fr) 2010-12-23 2016-06-29 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Circuit intégré multi-niveaux, dispositif et procédé pour modéliser des circuits intégrés multi-niveaux
US9672312B2 (en) * 2015-05-04 2017-06-06 Globalfoundries Inc. Method wherein test cells and dummy cells are included into a layout of an integrated circuit
KR102458446B1 (ko) * 2016-03-03 2022-10-26 삼성전자주식회사 스탠다드 셀을 포함하는 반도체 장치 및 그것의 전자 설계 자동화 방법

Also Published As

Publication number Publication date
US20190012420A1 (en) 2019-01-10
EP3425541A1 (fr) 2019-01-09
FR3068798A1 (fr) 2019-01-11
US10740528B2 (en) 2020-08-11
EP3425541B1 (fr) 2021-08-25

Similar Documents

Publication Publication Date Title
FR3068798B1 (fr) Procede de generation d'un agencement de circuit 3d a partir d'un agencement de circuit 2d
CL2022001370A1 (es) Método y aparato para conexión en cadena de módulos fotovoltaicos, dispositivo y medio de almacenamiento
US20130163467A1 (en) Shortest path determination for large graphs
WO2007044383A3 (fr) Systeme et procede d'optimisation multifactoriel
RU2011108546A (ru) Устройство передачи данных, программа генерирования данных передачи и способ генерирования данных передачи
MY168566A (en) Method for manufacturing crystalline silicon solar cell, method for manufacturing solar cell module, crystalline silicon solar cell, and solar cell module
EP3588282A3 (fr) Appareil et procédé pour une conversion cohérente et accélérée entre des représentations de données
PH12019501832A1 (en) Improving blockchain transaction speeds using global acceleration nodes
ATE369629T1 (de) Kapselungsstruktur für abbildungsdetektoren
EA201690827A1 (ru) Модульный лазерный аппарат
GB2600872A (en) System-aware selective quantization for performance optimized distributed deep learning
EA201791413A1 (ru) Размещение контроллера памяти в трехмерной (3d) интегральной схеме (ic) (3dic) с использованием распределенных массивов переходных отверстий в кремнии (tsv)
Liem et al. Molecular dynamics simulations on distributed memory machines
CN106461761A (zh) 距离图像传感器
FR3102272B1 (fr) Génération périodique de fonction aléatoire dans le nuage informatique
AU2020369825B2 (en) 3D neural inference processing unit architectures
El Marghichi et al. Electrical parameters identification for three diode photovoltaic based on the manta ray foraging optimization with dynamic fitness distance balance
CN104182407A (zh) 一种缩小数据查找范围的数据处理系统
FR3084961B1 (fr) Dispositif memoire
FR3037427B1 (fr) Procede et dispositif de recherche d’un lieu
CN100480971C (zh) 导航位置的光学传感装置及其导航方法
WO2016148793A1 (fr) Optimisation de conceptions d'interconnexion dans des circuits intégrés à faible puissance (ics)
Iimura et al. Consideration on distributed immune algorithm in jobshop scheduling problem
FR3082968B1 (fr) Procede de protection d'un fpga contre des radiations naturelles
JP2014035304A (ja) 情報取得装置および物体検出装置

Legal Events

Date Code Title Description
PLSC Publication of the preliminary search report

Effective date: 20190111

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

ST Notification of lapse

Effective date: 20230305