FR3062234B1 - Procede de fabrication d'un dispositif memoire - Google Patents

Procede de fabrication d'un dispositif memoire Download PDF

Info

Publication number
FR3062234B1
FR3062234B1 FR1750594A FR1750594A FR3062234B1 FR 3062234 B1 FR3062234 B1 FR 3062234B1 FR 1750594 A FR1750594 A FR 1750594A FR 1750594 A FR1750594 A FR 1750594A FR 3062234 B1 FR3062234 B1 FR 3062234B1
Authority
FR
France
Prior art keywords
electrode
memory device
manufacturing
face
change
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1750594A
Other languages
English (en)
Other versions
FR3062234A1 (fr
Inventor
Sophie BERNASCONI
Christelle Charpin-Nicolle
Aomar Halimaoui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, STMicroelectronics Crolles 2 SAS, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1750594A priority Critical patent/FR3062234B1/fr
Priority to US15/878,036 priority patent/US10651376B2/en
Publication of FR3062234A1 publication Critical patent/FR3062234A1/fr
Application granted granted Critical
Publication of FR3062234B1 publication Critical patent/FR3062234B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/25—Multistable switching devices, e.g. memristors based on bulk electronic defects, e.g. trapping of electrons
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02258—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of switching materials after formation, e.g. doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/828—Current flow limiting means within the switching material region, e.g. constrictions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0078—Write using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/52—Structure characterized by the electrode material, shape, etc.
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention concerne un dispositif mémoire comprenant une première électrode (27), une deuxième électrode (28) et une portion active à changement d'état conducteur disposée entre une première face de la première électrode (27) et une première face de la deuxième électrode (28). La première électrode (27) comprend une portion supérieure formant la première face de la première électrode (27). Au moins l'une parmi la portion supérieure et la portion active à changement d'état conducteur comprend une couche poreuse (15).
FR1750594A 2017-01-25 2017-01-25 Procede de fabrication d'un dispositif memoire Active FR3062234B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1750594A FR3062234B1 (fr) 2017-01-25 2017-01-25 Procede de fabrication d'un dispositif memoire
US15/878,036 US10651376B2 (en) 2017-01-25 2018-01-23 Method of manufacturing a memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1750594 2017-01-25
FR1750594A FR3062234B1 (fr) 2017-01-25 2017-01-25 Procede de fabrication d'un dispositif memoire

Publications (2)

Publication Number Publication Date
FR3062234A1 FR3062234A1 (fr) 2018-07-27
FR3062234B1 true FR3062234B1 (fr) 2020-02-28

Family

ID=58739083

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1750594A Active FR3062234B1 (fr) 2017-01-25 2017-01-25 Procede de fabrication d'un dispositif memoire

Country Status (2)

Country Link
US (1) US10651376B2 (fr)
FR (1) FR3062234B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11088323B2 (en) * 2018-08-30 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Top electrode last scheme for memory cell to prevent metal redeposit
JP2021150390A (ja) * 2020-03-17 2021-09-27 キオクシア株式会社 記憶装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3603188B2 (ja) * 2001-12-12 2004-12-22 松下電器産業株式会社 不揮発性メモリ及びその製造方法
WO2003096401A1 (fr) * 2002-05-14 2003-11-20 Matsushita Electric Works, Ltd. Procede d'oxydation electrochimique
KR100615586B1 (ko) * 2003-07-23 2006-08-25 삼성전자주식회사 다공성 유전막 내에 국부적인 상전이 영역을 구비하는상전이 메모리 소자 및 그 제조 방법
US7791141B2 (en) 2004-07-09 2010-09-07 International Business Machines Corporation Field-enhanced programmable resistance memory cell
TWI261915B (en) * 2005-01-07 2006-09-11 Ind Tech Res Inst Phase change memory and fabricating method thereof
KR100668333B1 (ko) * 2005-02-25 2007-01-12 삼성전자주식회사 Ｐｒａｍ 소자 및 그 제조방법
US7750386B2 (en) * 2008-11-12 2010-07-06 Seagate Technology Llc Memory cells including nanoporous layers containing conductive material
US20130075685A1 (en) * 2011-09-22 2013-03-28 Yubao Li Methods and apparatus for including an air gap in carbon-based memory devices
US9299926B2 (en) * 2012-02-17 2016-03-29 Intermolecular, Inc. Nonvolatile memory device using a tunnel oxide layer and oxygen blocking layer as a current limiter element
US9218958B2 (en) 2013-12-10 2015-12-22 Infineon Technologies Ag Method for forming a semiconductor device
US9570576B2 (en) 2013-12-10 2017-02-14 Infineon Technologies Ag Method for forming a semiconductor device having insulating parts or layers formed via anodic oxidation
WO2016115601A1 (fr) * 2015-01-20 2016-07-28 Newsouth Innovations Pty Limited Procédé d'anodisation d'une surface d'un dispositif semi-conducteur

Also Published As

Publication number Publication date
US10651376B2 (en) 2020-05-12
FR3062234A1 (fr) 2018-07-27
US20180254414A1 (en) 2018-09-06

Similar Documents

Publication Publication Date Title
Chrom et al. Incorporating neutrophil-to-lymphocyte ratio and platelet-to-lymphocyte ratio in place of neutrophil count and platelet count improves prognostic accuracy of the international metastatic renal cell carcinoma database consortium model
EP2741332A3 (fr) Substrat de réseau et son procédé de fabrication
FR3062234B1 (fr) Procede de fabrication d'un dispositif memoire
US20170373071A1 (en) Vertical channel transistor-based semiconductor structure
FR3103630B1 (fr) Puce fonctionnelle adaptee pour etre assemblee a des elements filaires, et procede de fabrication d’une telle puce
Levitt et al. A digital master hearing aid.
Rømer Clinical and biochemical aspects of sarcoidosis. With special reference to angiotensin-converting enzyme (ACE).
TW200625486A (en) Bonding structure and fabrication thereof
FR3059157B1 (fr) Procede de fabrication d’une memoire resistive
JPWO2013024791A1 (ja) 化学・物理現象検出装置及び検出方法
Sauer et al. The prognostic value of the glycerol test: a review of 60 ears with unidirectional inner ear valve implants.
Parker Labyrinth and cerebral-spinal fluid pressure changes in guinea pigs and monkeys during simulated zero G.
FR3082033B1 (fr) Procede de fabrication d'un calculateur a reseaux de neurones recurrents
FR3077681B1 (fr) Batterie en couches minces
Molochkov et al. Chromoblastomycosis
FR3089056B1 (fr) Dispositif électronique comprenant un substrat de support et des puces électroniques, empilés
Pradat-Diehl et al. Conduction aphasia and phonemic disorder
JP6074770B2 (ja) 化学・物理現象検出方法及びその装置
Krejs et al. Esophageal function in progressive systemic sclerosis.
JP5002468B2 (ja) 半導体圧力センサ
FR3090196B1 (fr) Procede de fabrication d’une memoire ferroelectrique et procede de co-fabrication d’une memoire ferroelectrique et d’une memoire resistive
Arndt et al. Prediction of speech understanding with the transcutaneous partially implantable bone conduction hearing system Osia®. German Version
Abel et al. Speech intelligibility in noise with ear protectors.
FR3081223B1 (fr) Dispositif de detection capacitive redondante parallele
Shrestha et al. Noise-induced hearing loss among patients requiring pure tone audiometry evaluation in a tertiary care centre: a descriptive cross-sectional study

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20180727

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8