FR3023978A1 - OPTOELECTRONIC DEVICE WITH ELECTROLUMINESCENT DIODE - Google Patents

Abstract

The invention relates to an optoelectronic device (35) comprising a support (40) comprising a face (14); and a light-emitting diode on said face and comprising a stack of semiconductor layers (16, 18, 20) of non-centrosymmetric crystalline semiconductor materials, the light-emitting diode having an active region (18) comprising a single quantum well or quantum wells multiple, the active area being stressed, the maximum relative deformation in the active zone being, in absolute value, between 0.1% and 5%.

Description

TECHNICAL FIELD The present invention relates generally to optoelectronic devices based on semiconductor materials and to their manufacturing processes. BACKGROUND OF THE INVENTION The present invention relates more particularly to optoelectronic devices comprising light-emitting diodes. PRESENTATION OF THE PRIOR ART It is known to produce a light-emitting diode whose active area comprises a single quantum well or multiple quantum wells. A quantum well is formed by interposing, between a first layer of a first P type doped semiconductor material and a second layer of the first N type doped semiconductor material, a layer of a second semiconductor material whose band gap is different from that of the first and second layers. The wavelength of the light emitted by the light-emitting diode depends in particular on the forbidden band of the second material. The light output of the active zone is the ratio between the luminous flux emitted by the active zone and the electrical power supplied to the light-emitting diode. The first and second materials may comprise mainly III-V compounds, for example GaN and B13251-DD15161JBD 2 InGaN. However, it can be observed with this type of structure, especially when the first and second materials are non-centrosymmetric materials with growth along a polar axis, for example the c axis in the case of a hexagonal structure, variations the emission wavelength and the light output, especially when the growth of the semiconductor layers forming the light emitting diode is carried out by epitaxy in the direction c. However, the use of III-V compound materials is desirable inasmuch as there are methods of epitaxially growing such materials on substrates over large areas and at low cost. SUMMARY Thus, an object of one embodiment is to overcome at least in part the disadvantages of the single quantum well or quantum well quantum well light emitting diode optoelectronic devices described above and their methods of manufacture. Another object of an embodiment is that the light emitting diode comprises a stack of semiconductor material layers based on III-V compounds. Another object of an embodiment is to increase the light output of the active zone of the light-emitting diode. Another object of an embodiment is to control the wavelength of the radiation emitted by the active area. Thus, an embodiment provides an optoelectronic device comprising: a support comprising a face; and a light emitting diode on said face and comprising a stack of semiconductor layers of non-centrosymmetric crystalline structure semiconductor materials, the light emitting diode having an active region comprising a single quantum well or multiple quantum wells, the active area being constraint, B13251 - DD15161JBD 3 the maximum relative deformation in the active zone being, in absolute value, between 0.1% and 5%. According to one embodiment, the face comprises at least one concave or convex portion and the light-emitting diode 5 matches the shape of the concave or convex portion. According to one embodiment, each semiconductor layer is predominantly a compound III-V, a compound II-VI, or a combination of at least two of these compounds. According to one embodiment, each semiconductor layer is predominantly of a compound InxAlyGai_x_yN where 0Kx1, (iKyl and 1-xy> 0. According to one embodiment, the optoelectronic device comprises a support layer of a metallic material, insulating or In one embodiment, the semiconductor layers are composed predominantly of III-V compounds and the semiconductor layers are formed by epitaxy with the polarity of the semiconductor layer being formed by epitaxy from the support layer. the V element, the active zone being in tension or the semiconductor layers are formed by epitaxy with the polarity of the element III, the active zone being in compression According to one embodiment, said stack comprises first and second semiconductor layers sandwiching the active zone, the first semiconductor layer being of a first semi material doped conductor of a first conductivity type and the second semiconductor layer being first doped semiconductor material of a second conductivity type opposite to the first type. An embodiment also provides a method of manufacturing an optoelectronic device comprising forming on a substrate a light emitting diode comprising a semiconductor layer stack of non-centrosymmetric crystal structure semiconductor materials, the light emitting diode having a region B13251 - DD15161JBD 4 active comprising a single quantum well or multiple quantum wells, the active zone being stressed, the maximum relative deformation in the active zone being, in absolute value, between 0.1% and 5%.

According to one embodiment, the method comprises the following steps: thinning the substrate at least at the level of the stack; and deforming the substrate and the stack to stress the active zone, the maximum relative deformation of the active zone being in absolute value between 0.1% and 5%. According to one embodiment, at the deformation step, the substrate is sandwiched between first and second pieces, at least one of the first or second pieces comprising a protrusion or an imprint. According to one embodiment, said protrusion comprises a deformable material. According to one embodiment, the thinning step comprises etching an opening in the substrate on the opposite side of the stack. According to one embodiment, the thinning step comprises fixing a handle on the side of the stack and thinning the entire substrate. According to one embodiment, the method comprises the following steps: forming a support layer on the substrate; stressing said support layer; and attaching the stack to said support layer. In one embodiment, the method comprises ionically bombarding the support layer. According to one embodiment, the support layer has a coefficient of thermal expansion different from the coefficient of thermal expansion of the semiconductor layers of the stack.

B13251 - DD15161JBD Brief description of the drawings These features and advantages, as well as others, will be set forth in detail in the following description of particular embodiments in a non-limitative manner with reference to the accompanying drawings in which: FIGS. 3 are sectional, partial and schematic views of embodiments of a light emitting diode; FIG. 4 is a partial, schematic sectional view of an embodiment of a multiple quantum well light emitting diode active area; Figures 5 to 7 show the energy band diagrams in the light emitting diode shown in Figure 2 or 3 for different levels of mechanical stress applied to the active area of the light emitting diode; FIGS. 8 to 10 show evolution curves of the charge carrier wave functions in the light-emitting diode shown in FIG. 2 or 3 for different levels of mechanical stresses applied to the active zone of the light-emitting diode; FIGS. 11 to 13 show evolution curves of the radiative recombination rates of the quantum well of the light-emitting diode shown in FIG. 2 or 3 for different levels of mechanical stresses applied to the active zone of the light-emitting diode; FIG. 14 represents curves of evolution of the radius of curvature of a layer as a function of the maximum relative deformation of the layer for several layer thicknesses; FIG. 15 shows curves of evolution of the deflection of a layer as a function of the radius of curvature of the layer for several layer lengths; Figs. 16 and 17 are respectively a perspective and a sectional view, partial and schematic, of an embodiment of an optoelectronic device comprising a light emitting diode; B13251 - DD15161JBD 6 Figures 18 and 19 are sectional views, partial and schematic, of other embodiments of an optoelectronic device; FIGS. 20A to 20F are sectional, partial and schematic views of structures obtained at successive stages of an embodiment of a method of manufacturing the optoelectronic device shown in FIG. 17; and FIGS. 21A to 21E are partial and schematic sectional views of structures obtained at successive steps of an embodiment of a method of manufacturing the optoelectronic device shown in FIG. 19. Detailed Description For the sake of clarity , of the same elements have been designated with the same references in the different figures and, moreover, as is customary in the representation of the electronic circuits, the various figures are not drawn to scale. In addition, only the elements useful for understanding the present description have been shown and are described. In particular, the means for biasing an electroluminescent diode of an optoelectronic device are well known and are not described. In the rest of the description, unless otherwise indicated, the terms "substantially", "about" and "of the order of" mean "to within 10%". The active region of the light-emitting diode is the region from which the majority of the electromagnetic radiation provided by the light-emitting diode is emitted. In the remainder of the description, a non-centrosymmetric material is a monocrystalline material which has no atom in the center of the crystal mesh. The crystallographic structure is not symmetrical, which induces an asymmetry of the electric charges. Figures 1 to 3 show an embodiment of a light emitting diode structure 10 having a stack 12 of semiconductor layers having a thickness e. Stack 12 comprises successively from bottom to top: a support layer 14; B13251 - DD15161JBD 7 a semiconductor layer 16 doped with a first type of conductivity, for example doped N type; an active area 18; and a doped semiconductor layer of a second type of conductivity opposite the first type of conductivity, for example doped P-type. The stack of the semiconductor layer 16, the active zone 18 and the semiconductor layer 20 is called active stacking. 21 in the following description. According to one embodiment, the materials making up the active zone 18 and the semiconductor layers 16 and 20 are piezoelectric semiconductor materials with a non-centrosymmetric structure. By way of example, the active zone 18 and the semiconductor layers 16 and 20 may each comprise in majority a non-centrosymmetric compound comprising a group III element and a group V element, hereinafter called III-V compound, a compound comprising a group II element and a group VI element, hereinafter referred to as II-VI compound, or a combination of at least two of these compounds. According to one embodiment, the active zone 18 and the semiconductor layers 16 and 20 each mainly comprise a non-centrosymmetric III-V compound, especially a III-N compound. Examples of group III elements include gallium (Ga), indium (In) or aluminum (Al). According to one embodiment, the active zone 18 and the semiconductor layers 16 and 20 each mainly comprise InxAlyGal_x_yN (OKx1, OKyl and 1-x-y> 0). Examples of III-N compounds are GaN, AlN, InN, InGaN, AlGaN or AlInGaN. Other Group V elements may also be used, for example, phosphorus or arsenic. In general, the elements in compound III-V can be combined with different mole fractions. According to one embodiment, the active zone 18 and the semiconductor layers 16 and 20 each mainly comprise a non-centrosymmetric compound II-VI. Examples of group II elements include elements of the HA group, especially beryllium (Be) and magnesium (Mg) and elements of group IIB, especially zinc (Zn) and cadmium (Cd). . Examples of Group VI elements include elements of the VIA group, including oxygen (O) and tellurium (Te). Examples of compounds II-VI are ZnO, ZnMgO, CdZnO or CdZnMgO. In general, the elements in II-VI can be combined with different mole fractions. The semiconductor layers 16 and 20 and the active zone 18 may each comprise a dopant. By way of example, for compounds III-V, the dopant may be chosen from the group comprising a Group II P dopant, for example magnesium (Mg), zinc (Zn), cadmium (Cd ) or mercury (Hg), a group IV P-type dopant, for example carbon (C) or a group IV N-type dopant, for example silicon (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb) or tin (Sn). The active area 18 may comprise a single quantum well. It comprises a semiconductor material different from the semiconductor material forming the layers 16 and 20 and having a band gap smaller than that of the layers 16 and 20. The active zone 18 may comprise multiple quantum wells. It then comprises a stack of semiconductor layers forming an alternation of quantum wells and barrier layers.

The thickness of the semiconductor layer 16 may be between 0.1 fun and 20 pin. The thickness of the semiconductor layer 20 may be between 50 nm and 20 μm. The thickness of the active zone 18 may be between 10 nm and 500 nm.

The support layer 14 may be of a semiconductor material, for example silicon, germanium, silicon carbide, a III-V compound, such as GaN or GaAs, or a ZnO substrate. Preferably, the layer 14 is monocrystalline silicon. Preferably, the layer 14 is made of a semiconductor material compatible with the manufacturing processes implemented in microelectronics. The support layer 14 may be of a conductive material, for example a metal, especially tungsten or molybdenum. The support layer 14 may be made of an insulating material, for example sapphire (Al 2 O 3), silicon carbide (SiC), diamond, glass, silica (SiO 2), silicon (Si) or a silicon structure on Insulator (SOI). The thickness of the support layer 14 may be between 1 and 5 mm. The thickness of the stack 12 may be between 10 1 gm and 5 mm. According to one embodiment, the layers 16 and 20 and the semiconductor layer or the semiconductor layers of the active area 18 are epitaxially formed on the support layer 14. Alternatively, an undoped semiconductor layer may be present between the support layer 14 and the semiconductor layer 16 and forms a buffer zone which makes it possible to epitaxially grow the semiconductor layer 16. The fact that a material based on at least a first element and a second element has a polarity of the first element or a polarity of the second element means that when the material is epitaxially formed on a support, it grows in a preferred direction and when the material is cut in a plane perpendicular to the preferred growth direction, the exposed face of the remaining part of the material 25 on the support essentially comprises atoms of the first element in the case of the polarity of the first element or atoms of the second element in the case of the polarity of the second element. According to one embodiment, the active zone 18 and the semiconductor layers 16 and 20 mainly comprise piezoelectric semiconductor materials having a spontaneous polarization. According to one embodiment, the growth direction of the semiconductor layers of the active stack 21 is not perpendicular to the direction of the electric field due to the spontaneous polarization.

In the case of semiconductor layers 16, 18, composed mainly of a III-V compound, the crystalline structure of the layers may be hexagonal, for example of the wurtzite type.

By way of example, in the case where the semiconductor layers 16, 18, 20 mainly comprise a III-V compound, the direction of growth of the layers is the direction c. More precisely, in the case where the semiconductor layers comprise mainly a compound III-V and are of polarity of the element V, the direction of growth of the semiconductor layers of the stack corresponds to the crystallographic direction [000-1], also called -c direction. In the case where the semiconductor layers comprise mainly a compound III-V and are of polarity of the element III, the growth direction of the semiconductor layers of the stack corresponds to the crystallographic direction [0001], also called direction + c. FIG. 4 represents an enlarged view of a portion of the light emitting diode structure 10 according to an embodiment in which the active area 18 comprises a multiple quantum well structure including, for example, alternating GaN layers. And layers of InGaN 32, two layers of InGaN 32 and three layers of GaN 30 being shown in FIG. 4. By way of example, each layer of GaN has a thickness ranging from 2 to 40 nm (for example 8 nm) and each InGaN layer has a thickness ranging from 0.5 to 20 nm (for example 2.5 nm). According to one embodiment, the active zone 18 of the light-emitting diode is put under tension or in compression.

This can be done, as illustrated in FIG. 1, by providing in the stack 12 a layer placed under stress which, by its intrinsic mechanical stress, will apply a stress to the stack 12 forming the light emitting diode. By way of example, a layer produced under ion bombardment will induce a mechanical compressive stress in the stack 11. According to one embodiment, the support layer 14 may have a multilayer structure and the additional constrained layer may be part of the support layer 14.

By way of example, by the ion beam sputtering technique or IBS (Ion Beam Sputtering), the stress in a silica layer, deposited in this way with a thickness of less than 1 pin, can reach 1 GPa and impose this constraint on the stack 12 forming the light-emitting diode. The stress in a layer of silicon nitride (Si3N4), deposited in the same way with the same thickness, can reach 1.8 GPa. If, on the other hand, the layer is bombarded with ions during growth, in particular by double ion beam reactive sputtering or DIBS (Dual Ion Beam Sputtering), the compression stress in this layer is further increased. . Thus, a 0.25 μm thick layer of diamond-like carbon bombarded with argon ions with an energy of 100 eV has a compressive stress state of 2.5 GPa. In the same way, a zinc oxide layer made by evaporation can have a stress in tension. Another way of applying this mechanical stress to the device and the active zone 18 in particular is to fix the stack 12, for example by gluing, a layer whose expansion coefficient is different from the expansion of the device. The bonding may be bonding material, for example an epoxy adhesive, bonding, for example by molecular bonding. If the bonding is done in such a way coefficient realized with one or without material at room temperature, there is no stress in the stack 12, it is possible to obtain the desired stress during operation: when the device will heat up, the differences in coefficient of expansion will put the device in constraint. This deformation may, in addition, be controlled during the operation of the light-emitting diode, for example by a thermal module connected to a temperature sensor and adapted to modify the intensity of the electric current supplying at least some components of the device. Optoelectronics as a function of the measured temperature. According to one embodiment, the support layer 14 may have a multilayer structure and the additional layer with a different coefficient of expansion may be part of the support layer 14. For example, a silica layer has a coefficient of thermal expansion of 0.5 10-6 K-1 and gallium nitride has a coefficient of thermal expansion of the order of 5.10-6 K-1. For a GaN Young modulus of 500 GPa, and for a temperature difference of 100 ° C., which corresponds to a typical heating of a light emitting diode during operation, the induced stress is a compressive stress and is equal to 225 MPa . For a layer of HfO 2, which has a coefficient of thermal expansion of 10 × 10 -6 K -1, a voltage stress in GaN of 250 MPa is induced in the active stack 21. Another way of stressing the active zone 18 is to form the stack 12 of semiconductor layers on a flat surface so that the interfaces between the layers 14, 16, 18, 20 substantially correspond to parallel planes, and to deform the stack 12 obtained, in particular by applying a curvature, to put the active zone 18 in tension or in compression. According to one embodiment, after deformation, the stack 12 may have a symmetry of revolution. The stack can then have the shape of a spherical cap. According to one embodiment, after deformation, the stack 12 may have a planar symmetry. The stack can then have the shape of a cylindrical sector. In the section plane of FIG. 2 or 3, the neutral line N is the line of the stack 12 where the deformation is zero. In the remainder of the description, arrow F is the maximum distance between the neutral line N and a reference plane Pref. In FIG. 2 or 3, the edge of the stack 12 rests on the B13251 - DD15161JBD 13 reference plane Pref. As a variant, the reference plane Pref may be a plane tangent to the neutral line N. The average radius of curvature Rm of the stack 12 is the radius of curvature equal to the average of the radius of curvature of the neutral line N. In the case where the deformed stack 12 corresponds to a spherical cap, the radius of curvature of the neutral line N is constant and equal to the mean radius of curvature Rm. The average center of curvature of the stack 12 is called 0. In the case where the edge of the stack 12 rests on the reference plane Pref, it is called chord C of the stack 12 the distance between the contact points of the stack 12 and the reference plane Pref in the plane of chopped off. The deformation applied to the stack 12 in FIG. 2 or 3 results in the development of mechanical stresses in the layers of the stack 12. In the embodiment represented in FIG. 2, the layers located below the neutral line N are stretched and in a state of tension stress and the layers above the neutral line N are compressed and in a state of compressive stress. In the embodiment shown in Figure 3, the layers below the neutral line N are in compression and the layers above the neutral line N are stretched. The inventors have demonstrated that the wavelength of the radiation emitted by the active zone 18 can be controlled as a function of the mechanical stresses applied to the active zone 18. FIGS. 5, 6 and 7 represent the diagrams of energy, determined by simulation, of the semiconductor layers 16, 18, 20 of the light-emitting diode 10 respectively in the absence of deformation, when the active zone 18 is in tension and when the active zone 18 is in compression. For these simulations, the layer 16 was doped GaN type N with a dopant concentration equal to 1019 atoms / cm3. Active zone 18 was a single quantum well comprising an InGaN layer with an atomic percentage of indium of 16% and B13251 - DD15161JBD 14 having a thickness of 1.5 nm. Layer 20 was P type doped GaN with a dopant concentration of 1019 atoms / cm3. The layers 16, 18 and 20 were epitaxially formed on the support layer 14 in the -c direction with a N polarity.

The band diagrams were obtained with a current flow through the light emitting diode of 100 A / cm 2. In FIGS. 5 to 7, the N-type doped GaN 16 layer, the InGaN 18 layer and the P-type doped GaN 20 layer are delimited by two vertical lines. The distances indicated on the abscissa axis are measured from a reference plane. In FIGS. 5 to 7, the curves BV16, BV18 and BV20 represent the upper limit of the valence band respectively in the layers 16, 18 and 20 and the curves BC16, BC18 and BC20 represent the lower limit of the conduction band respectively in the layers 16, 18 and 20. The curve EH represents the bound state energy of a hole in the active zone 18 and the curve EE represents the bound state energy of an electron in the active zone 18 The wavelength of the radiation emitted by the active zone 18 is proportional to the difference AE between the energy levels EH and EE. The stressing of the stack 12 leads to the formation of an electric field across the active zone 18 which modifies the distribution of the energy bands and therefore the wavelength of the emitted radiation.

Figure 5 was obtained when the stack 12 was not deformed. The difference AE obtained was 2.93 eV, which corresponds to a radiation whose wavelength was 423 nm. FIG. 6 was obtained when the active zone 18 was under tension with a maximum relative deformation of 2%.

The difference AE obtained was 2.96 eV, which corresponds to a radiation whose wavelength was 418 nm. A decrease in length was thus obtained with respect to an undistorted stack 12. FIG. 7 was obtained when the active zone 18 was under compression with a maximum relative deformation of 2%. The difference AE obtained was 2.8 eV, B13251 - DD15161JBD which corresponds to a radiation whose wavelength was 443 nm. An increase in length was thus obtained with respect to an undistorted stack 12. In general, in the case of a stack 12 of semiconductor layers each comprising in majority a compound III-V, formed on the support layer 14 with the polarity of the element V, the wavelength of the radiation emitted by the active area 18 is decreased when the active area 18 is in tension and is increased when the active area 18 is in compression.

The inventors have also demonstrated that, in the case of a stack 12 of semiconductor layers each comprising mainly a compound III-V, formed on the support layer 14 with the polarity of the element III, the wavelength radiation emitted by the active zone 18 is increased when the active zone 18 is in tension and is decreased when the active zone 18 is in compression. The inventors have furthermore demonstrated that the luminous efficiency of the active zone 18 could be modified as a function of the mechanical stresses applied to the active zone 18. FIGS. 8, 9 and 10 represent the evolution curve CE of the electron-bound state wave function and the evolution curve CH of the bound state wave function of a hole in the layers 16, 18, 20 determined by simulation for the diode 10 respectively in the absence of deformation, when the active zone 18 is in tension and when the active zone 18 is in compression under the same conditions as those used respectively to obtain Figures 5, 6 and 7. FIGS. 11, 12 and 13 represent the evolution of the radiative recombination rate Tx, which is representative of the light efficiency, in the layers 16, 18, 20 determined by simulation for the light-emitting diode respectively in the absence of deformation, when the active zone 18 is involtage and when the active zone 18 is in compression in the same conditions as those used respectively for obtaining FIGS. 5, 6 and 7. The stressing of the stack 12 leads to the formation of an electric field across the active zone 18 5 which modifies the overlap of the wave functions and therefore the luminous efficiency of the active zone 18. FIGS. 8 and 11 were obtained when the stack 12 was not deformed . Due to the crystallographic nature of the III-V compounds and the epitaxial growth direction of the layers 16, 18 and 20, spontaneous polarization occurs which results in the formation of an electric field in the active zone 18. The result is , by quantum confined Stark effect, an offset of the bound state wave function of the electron to the P-type doped GaN layer 20 and an offset of the bound state wave function of the hole to the layer 16 of type N doped GaN. FIGS. 9 and 12 were obtained when the active zone 18 was under tension with a maximum relative deformation of 2%. The electric field which is formed by piezoelectric effect in the active zone 18 increases the overlap between the wave functions which leads to an increase in the radiative recombination rate of 45% compared to the case without deformation. Figures 10 and 13 were obtained when the active zone 18 was under compression with a maximum relative deformation of 2%. The electric field which is formed by piezoelectric effect in the active zone 18 decreases the overlap between the wave functions, which leads to a reduction in the radiative recombination rate of two orders of magnitude compared to the case without deformation. In general, in the case of a stack 12 of semiconductor layers each comprising in majority a compound III-V, formed on the support layer 14 with the polarity of the element V, the luminous efficiency is increased when the active zone 18 is put in tension.

The inventors have also demonstrated that, in the case of a stack 12 of semiconductor layers each comprising mainly a compound III-V, formed on the support layer 14 with the polarity of the element III, the light output is increased when the active zone 18 is put into compression. According to one embodiment, when the stack 12 is deformed, the active zone 18 is not on the neutral line N so as to be put in full tension or compression. The value of the deformation in the active zone 18 depends on the distance of the active zone 18 from the neutral line N of the stack 12 and therefore the thickness e of the stack 12. The deformation applied to the stack 12 is chosen so that the stresses that appear in the materials of the layers 14, 16, 20 and the active zone 18 are less than the elastic limit of these materials so as not to cause breakage in these materials during the deformation. For GaN and InGaN, the yield strength corresponds to a maximum relative strain Ej equal to about 5%. According to one embodiment, the maximum relative deformation smAx applied to the stack 12 varies, in absolute value, from 0.1% to 2.5%, preferably from 1% to 2%. Obtaining the desired maximum relative deformation smAx 25 is obtained by varying the thickness e of the stack and the average radius of curvature Rm of the stack 12. FIG. 14 represents evolution curves C1 to C7 of FIG. mean radius of curvature Rm, in logarithmic scale, of a stack 12 as a function of the maximum relative deformation 30 weeks, dimensionless, of the stack 12 for thicknesses e of the stack 12 respectively of 2 pin, 4 gm, 6 gm, 8 gm, 10 gm, 50 gp and 100 gm. For a given maximum relative deformation smAx, the greater the thickness e, the higher the average radius of curvature Rm.

FIG. 15 shows evolution curves E1 to E6 of the logarithmic scale arrow F of the stack 12 for C-ropes in a cross-sectional plane respectively of 100 μm, 250 μm and 500 μm. , 750 μm, 1 mm and 2 mm.

The amplitude of the deflection of the neutral line N of the stack 12 must be sufficient to obtain the desired deformation of the active zone 18. Typically, the arrow must be greater than 1 / 20th of the rope C of the For example, for a stack 12 whose rope C is equal to 1 mm, the arrow F is at least 50 fun and for a stack 12 whose rope C is equal to 250 pin, the arrow F is at least 12.5 pin. The arrow is measured, for example, with respect to a plane containing the ends of the neutral line N before deformation. The average radius of curvature Rm of the stack 12 is between 0.5 and 3 mm for a stack 12 having a rope C of 1 mm and a thickness e of the order of 6 pin corresponding to a relative deformation of 0, 5 to 0.1% which induces an arrow of between 0.5 mm and 40 pin. To obtain a relative deformation of up to 2.5% with a stack 12 having a 1 mm rope C, and considering a hemispherical shape such as the maximum deformation with a mean radius of curvature Rm greater than 0.5 mm, it is necessary to have a thickness greater than 25 pin. A thickness of 100 pin makes it possible to obtain the same relative deformation of 2.5% with a radius of curvature of 2 mm or an arrow of only 63 pin. The radius of curvature of the stack 12 may not be constant. The radius of curvature Rm of the stack 12 is between 125 μm and 3 mm for a stack 12 having a C-shaped rope of 250 μm and a thickness of the order of 6 μm, corresponding to a relative strain of 2.5 μm. at 0.1%. In the section plane of FIG. 2 or 3, the length of the arc formed by the neutral line N of the stack 12 is greater than 1.007 mm for a stack 12 having a rope of 1 mm and 252 pin for a stack. 12 having a rope of 250 pm 35 (where the arrow is equal to 1 / 20th of the rope).

B13251 - DD15161JBD 19 Figures 16 and 17 are respectively a perspective view and a schematic partial sectional view of an embodiment of an optoelectronic light-emitting diode device 35 comprising: a conductive support 40 including a bottom face 42 and an upper face 44 comprising a convex portion 46, also called convex portion thereafter; an insulating region 48 on the face 44 around convex portion 46; the previously described stack 12 maintained in deformed configuration by the convex portion 46, the support layer 14 resting on the convex portion 46; a conductive layer 50 covering the layer 20 and comprising a portion 52 extending over the insulating region 48; a conductive pad 54 in contact with the portion 52, the pad 54 may further extend over a portion of the convex portion of the conductive layer 50; a base 56 comprising a plane upper face 58 on which is fixed the support 40 and a flat bottom face 60 opposite to the upper face 58; a via 62 through the base 56 and connected to the rear face 42 of the support 40, for example by a conductive region 64 extending on the upper face 58 and between the support 40 and the base 56, the via 62 being made of a material electrical conductor 25 and being isolated from the base 56; a via 66 through the base 56 and connected to the pad 54, for example by a conductive region 68 extending on the face 58 and a conductive wire 70, the via 66 being made of an electrically conductive material and being isolated from the base 56; A contact pad 72 on the face 60 connected to the via 62; and a contact pad 74 on the face 60 connected to the via 66. In the embodiment shown in FIGS. 16 and 17, the polarization of the light emitting diode is achieved by the application of a voltage between the contact pad B13251 - DD15161JBD 72, electrically connected to the semiconductor layer 16, and the contact pad 74, electrically connected to the semiconductor layer 20. The support 40 may have a one-piece structure or consist of several elements. The conductive layer 50 acts as an electrode and is adapted to polarize the active zone 18 of the light-emitting diode and to let the electromagnetic radiation emitted by the light-emitting diode pass. The material forming layer 50 may be a transparent and conductive material such as indium tin oxide (ITO), aluminum doped zinc oxide or graphene. . By way of example, the layer 50 has a thickness of between 5 nm and 200 nm, preferably between 20 nm and 50 nm. The insulating region 48 may be of a dielectric material, for example silicon oxide (SiO2), silicon nitride (SixNy, where x is approximately equal to 3 and y is approximately equal to 4, for example Si3N4), silicon oxynitride (SiOxNy where x may be about 1/2 and y may be about 1, eg Si2ON2), aluminum oxide (Al2O3), hafnium oxide (HfO2), or diamond. For example, the thickness of the insulating region 48 is between 5 nm and 500 nm, for example equal to about 100 nm. The optoelectronic device 35 may, in addition, comprise an encapsulation layer covering the entire structure and in particular the conductive layer 50. The optoelectronic device 35 may further comprise a phosphor layer, not shown, provided on the layer 30 of encapsulation or confused with it. FIG. 18 is a partial schematic sectional view of another embodiment of an optoelectronic device 80 comprising a conductive pad 82 on the face 44 and a conductive region 84 on the face 58 in contact with the via. and connected to the conductive pad 82 by a conducting wire 86.

According to one embodiment, the support 40 is electrically insulating. The electronic device may then comprise a conductive layer covering the face 44 of the support 40 and the conductive pad 82 can then be directly in contact with this conductive layer. FIG. 19 is a partial schematic sectional view of another embodiment of an optoelectronic device 88 with a light emitting diode. The optoelectronic device 88 comprises all the elements of the device 35 shown in Figure 17 with the difference that the curved portion 46 is replaced by a recessed portion 89, also called concave portion thereafter. The variant shown in FIG. 19 can also be implemented with the embodiment shown in FIG. 18. In the case where the support layer 14 is electrically non-conductive, the polarization of the light-emitting diode can be carried out via a conductive intermediate layer. disposed between the layer 14 and the semiconductor layer 16. According to one embodiment, the manufacturing method of the optoelectronic device embodiments described above successively comprises the formation of the stack 12 while the latter is substantially flat and the deformation of the stack 12. Figs. 20A to 20F illustrate an embodiment of a method of manufacturing the optoelectronic device 35. This embodiment comprises the following steps: (1) Formation of the active stack 21 on a substrate 90 (Figure 20A). In the present embodiment, the substrate 90 comprises the support layer 14 described above which covers a layer 92 of an insulating material, for example silicon dioxide, itself covering a plate 94 of a semiconductor material, for example example of silicon. The thickness of the dielectric layer 92 may be between 50 nm and 10 μm.

B13251 - DD15161JBD 22 The thickness of the plate 94 can be between 525 fun and 2 mm. Several light-emitting diodes may be formed on the substrate 90. An insulating layer 95 covers the layer 14 around the active stack 21.

By way of example, the active stack 21 can be obtained by forming the layers 16, 18 and 20 by epitaxy, for example by metalorganic chemical vapor phase epitaxy (MOCVD), on the whole of the layer 14, by etching these layers, for example by plasma etching, chemical etching or laser cutting, to delimit the active stack 21. According to another example, the insulating layer 95 can be deposited on the entire layer 14 and an opening may be formed in the insulating layer 95, the active stack 21 then being formed in the opening. (2) Formation of the conductive layer 50 and the conductive pad 54 (FIG. 20B), for example by conformal deposition. (3) Engraving, for each light-emitting diode, an opening 96 in the plate 94 and in the dielectric layer 92 to expose a portion of the layer 14 (Figure 20C) substantially opposite the active stack 21. The opening 96 is delimited by portions 98 of the dielectric layer 92 and the plate 94. The formation of the opening 96 may comprise first and second steps. The first step comprises etching the plate 94, the dielectric layer 92 can then act as an etch stop layer during the etching of the plate 94. The second step comprises etching the dielectric layer 92, the layer conductive 14 can then act as an etch stop layer during etching of the dielectric layer 92. In view from below, the opening 96 can occupy a surface of the order of 1 mm 2. The distance between the lateral flanks of two adjacent openings 96 may be of the order of 50 μm. (4) forming, for each optoelectronic device, a conductive region 100 on the face of the layer 14 exposed by the opening 96 (FIG. 20D). For example, the conductive region 100 is a metal region. The conductive region 100 may comprise a stack of layers. By way of example, the conductive region 100 may comprise a layer of a silicide in contact with the layer 14, for example nickel silicide (SiNi) or titanium silicide (TiSi 2), and a metal layer. (5) Deformation of the layer 14 and the active stack 21. Figure 20E is an exploded view of the shaping system of the layer 14 and the active stack 21. According to one embodiment, it is used an interposer 102 and a counter-mold 104. The interposer 102 may comprise a plate 106 on which is formed a block 108 of a deformable material for each light-emitting diode. Preferably, the block 108 and the plate 106 are each made of an electrically conductive material. By way of example, each block 108 is made of a solder material. Counter-mold 104 comprises, for each optoelectronic device, a cavity 110 having a shape complementary to the desired outer surface of the light-emitting diode. The deformation of the layer 14 and the active stack 21 is obtained by sandwiching the substrate 90 between the interposer 102 and the counter-mold 104, the block of deformable material filling the opening 96. A film 112 an elastomer may be interposed between the counter-mold 104 and the active stack 21 during the assembly step to increase the homogeneity of the mechanical stresses applied to the active stack 21. A conductive adhesive layer 114 may be provided between the interposer 106 and the substrate 90.

The volume of the block 108 is determined so that, when the substrate 90 is pressed against the plate 102, the opening 96 is completely filled with the material constituting the block 108 and the layer 14 and the active stack 21 are deformed in the form of the impression 110. Preferably, the assembly operation is performed at a temperature strictly lower than the melting temperature of the material constituting the blocks 108 and at a temperature greater than two thirds of the melting temperature of the material composing the blocks 108 expressed in Kelvin. By way of example, when the blocks 108 are made of a tin, silver and copper alloy of the SAC305 type, the assembly temperature may be greater than 55.degree. Before and after deformation, the chord of the deformed portion is substantially constant because the ends of this portion are blocked during the deformation.

According to another embodiment, the counter-mold 110 is pressed against the substrate 90 only at the locations where the active stack 21 is not present. This advantageously makes it possible not to apply pressure on the active stack 21.

According to another embodiment, the interposer 102 may correspond to a one-piece structure and be produced by machining or stamping. (6) Cutting the interposer 102 and the substrate 90 to separate the optoelectronic devices 35 (Fig. 20F).

The support 40 shown in FIGS. 17 and 19 corresponds to the assembly comprising the cut portion of the interposer 102, the cut portion of the layers 92 and 94 of the substrate 90 and the block 108. The method comprises subsequent steps of fixing 25 interposer 102 at the base 56. Figs. 21A-21E illustrate an embodiment of a method of manufacturing the optoelectronic device 88. This embodiment comprises the steps (1) and (2) described above. It further comprises the following steps: (3) Attaching a handle 120 to the conductive layer 50 (Fig. 21A). (4) Engraving plate 94 and dielectric layer 92 to expose layer 14 (FIG. 21B). The handle 120 advantageously allows handling of the layer 14 and the active stack 21.

B13251 - DD15161JBD (5) Application of the layer 14 to an interposer 122 having, for each optoelectronic device, a cavity 124 whose shape is complementary to the desired shape for the layer 14 and the active stack 21 (FIG. 21C ). An adhesive layer may be provided between the interposer 122 and the layer 14. (6) Removal of the handle 120 (Fig. 21D). (7) Deformation of the layer 14 and the active stack 21 (FIG. 21E). According to one embodiment, a counter-mold 126. A counter-mold 126 comprises, for each optoelectronic device, a protrusion 128 having a shape complementary to the desired outer surface of the light-emitting diode. The deformation of the layer 14 and the active stack 21 is obtained by sandwiching the layer 14 and the active stack 21 between the interposer 122 and the counter-mold 126. A film, not shown, an elastomer may be interposed between the counter-mold 126 and the layer 50 during the assembly step to increase the homogeneity of the mechanical stresses applied to the active stack 21.

Before and after deformation, the chord of the deformed portion is substantially constant because the ends of this portion are blocked during the deformation. The process continues with the cutting of the optoelectronic devices 88 and the fixing of the interposer 122 on the base 56.

According to one embodiment, several active stacks 21 can be formed on the same substrate 90 and the active stacks 21 can be deformed simultaneously before the cutting operation of the substrate 90. According to another embodiment, the substrate 90 is cut out. before the step of deformation of the active stacks 21. Each active stack 21 can then be deformed separately. According to one embodiment, the manufacturing method comprises a step of measuring the wavelength of the radiation emitted by the active zone 18 of the active stack 21 and a measurement of the light output of the active zone 18 before the step of B13251 - DD15161JBD 26 deformation. The amplitude of the deformation applied to the active zone 18, and therefore the selection of the volume of the block 108, the shape of the counter-mold 104, the interposer 122 and / or against the mold 126 is carried out to obtain the desired deformation of the active zone 18. This makes it possible to obtain the wavelength of the radiation emitted by the active zone 18 and / or the luminous efficiency of the active zone 18 desired.

Claims (16)

REVENDICATIONS1. An optoelectronic device (35,80; 88) comprising: a carrier (40) including a face (44); and a light-emitting diode (10) on said face and comprising a stack (21) of semiconductor layers (16, 18, 20, 30, 32) of non-centrosymmetric crystalline semiconductor materials, the light-emitting diode having an active region ( 18) comprising a single quantum well or multiple quantum wells, the active area being stressed, the maximum relative strain in the active zone being in absolute value between 0.1% and 5%. Optoelectronic device (35; 80; 88) according to claim 1, wherein the face (14) comprises at least one concave or convex portion (46; 96) and wherein the light-emitting diode (10) is in the form of the concave or convex portion. An optoelectronic device according to claim 1 or 2, wherein each semiconductor layer (16, 18, 20, 30, 32) is predominantly of a III-V compound, a II-VI compound, or a combination of at least two of these compounds. An optoelectronic device according to claim 3, wherein each semiconductor layer (16, 18, 20, 30, 32) is predominantly of an InxAlyGa1-x_yN compound where 0Kx1, 1: Ky1 and 1-x-y> 0. 25 Optoelectronic device according to any one of claims 1 to 4, comprising a support layer (14) of a metallic, insulating or semiconductor material resting on the face (14), the semiconductor layers (16, 18, 20, 30, 32) being epitaxially formed from the support layer (14). 30 Optoelectronic device according to claim 5, wherein the semiconductor layers (16, 18, 20, 30, 32) are composed mainly of III-V compounds and wherein the semiconductor layers are formed by epitaxy with the polarity of the element. V, the active region (18) being in tension or in which the semiconductor layers are epitaxially formed with the polarity of the element III, the active region (18) being in compression. Optoelectronic device according to any one of claims 1 to 6, wherein said stack (21) comprises first and second semiconductor layers (16, 20) sandwiching the active area (18), the first semiconductor layer ( 16) being of a first doped semiconductor material of a first conductivity type and the second semiconductor layer (20) being of the first doped semiconductor material of a second conductivity type opposite to the first type. A method of manufacturing an optoelectronic device (35; 80; 88) comprising forming on a substrate (40; 90) a light emitting diode comprising a stack (21) of semiconductor layers (16,18,20). 30, 32) into non-centrosymmetric crystal structure semiconductor materials, the light emitting diode having an active region (18) comprising a single quantum well or multiple quantum wells, the active region being stressed, the maximum relative deformation in the active zone being, in absolute value, between 0.1% and 5%. The method of claim 8, comprising the steps of: thinning the substrate (90) at least at the stack (21); and deforming the substrate and the stack to stress the active zone (18), the maximum relative deformation of the active zone being, in absolute value, between 0.1% and 5%. 30 The method of claim 9, wherein, at the deforming step, the substrate (90) is sandwiched between first and second pieces (102, 104; 122, 126), at least one of the first or second parts comprising a protrusion (108) or an impression (124) .B13251 - DD15161JBD 29 The method of claim 10, wherein said protrusion (108) comprises a deformable material. The method of any one of claims 9 to 11, wherein the thinning step comprises etching an aperture (96) in the substrate (90) on the side opposite the stack (21). The method of any one of claims 9 to 12, wherein the thinning step comprises attaching a handle (120) to the stack side (21) and thinning the entire substrate (90). The method of claim 8, comprising the steps of: forming a support layer (14) on the substrate (40); stressing said support layer; and attaching the stack (21) to said support layer. The method of claim 14 comprising ionically bombarding the support layer (14). The method of claim 14, wherein the support layer (14) has a thermal expansion coefficient different from the thermal expansion coefficient of the semiconductor layers (16, 18, 20, 30, 32) of the stack (21). ).