FR3019922B1 - Methode de realisation d'un reseau logique configurable - Google Patents
Methode de realisation d'un reseau logique configurableInfo
- Publication number
- FR3019922B1 FR3019922B1 FR1453310A FR1453310A FR3019922B1 FR 3019922 B1 FR3019922 B1 FR 3019922B1 FR 1453310 A FR1453310 A FR 1453310A FR 1453310 A FR1453310 A FR 1453310A FR 3019922 B1 FR3019922 B1 FR 3019922B1
- Authority
- FR
- France
- Prior art keywords
- producing
- configurable logic
- logic network
- network
- configurable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/10—Geometric CAD
- G06F30/18—Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1453310A FR3019922B1 (fr) | 2014-04-14 | 2014-04-14 | Methode de realisation d'un reseau logique configurable |
PCT/FR2015/050913 WO2015158984A1 (fr) | 2014-04-14 | 2015-04-08 | Méthode de réalisation d'un réseau logique configurable |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1453310A FR3019922B1 (fr) | 2014-04-14 | 2014-04-14 | Methode de realisation d'un reseau logique configurable |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3019922A1 FR3019922A1 (fr) | 2015-10-16 |
FR3019922B1 true FR3019922B1 (fr) | 2017-09-15 |
Family
ID=51518881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1453310A Active FR3019922B1 (fr) | 2014-04-14 | 2014-04-14 | Methode de realisation d'un reseau logique configurable |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR3019922B1 (fr) |
WO (1) | WO2015158984A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150176076A1 (en) | 2013-12-20 | 2015-06-25 | Acetylon Pharmaceuticals, Inc. | Histone deacetylase 6 (hdac6) biomarkers in multiple myeloma |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002230061A (ja) * | 2001-01-30 | 2002-08-16 | Matsushita Electric Ind Co Ltd | 半導体回路接続データベース及びこれを用いた半導体回路設計方法 |
US20070226572A1 (en) * | 2005-11-07 | 2007-09-27 | Ming Zhang | Soft error rate analysis system |
-
2014
- 2014-04-14 FR FR1453310A patent/FR3019922B1/fr active Active
-
2015
- 2015-04-08 WO PCT/FR2015/050913 patent/WO2015158984A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
FR3019922A1 (fr) | 2015-10-16 |
WO2015158984A1 (fr) | 2015-10-22 |
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Legal Events
Date | Code | Title | Description |
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PLFP | Fee payment |
Year of fee payment: 3 |
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PLFP | Fee payment |
Year of fee payment: 4 |
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CA | Change of address |
Effective date: 20171002 |
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CA | Change of address |
Effective date: 20171218 |
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CD | Change of name or company name |
Owner name: SAFRAN ELECTRICAL & POWER, FR Effective date: 20171218 |
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PLFP | Fee payment |
Year of fee payment: 5 |
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PLFP | Fee payment |
Year of fee payment: 7 |
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PLFP | Fee payment |
Year of fee payment: 8 |
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PLFP | Fee payment |
Year of fee payment: 9 |
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PLFP | Fee payment |
Year of fee payment: 10 |
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PLFP | Fee payment |
Year of fee payment: 11 |