FR2987699A1 - Microelectronic component for fully depleted silicon on insulator, has active zones formed by thin layer portion and thick layer portion, where thick layer portion is located directly above thin layer portion - Google Patents

Abstract

The component has an oxide coating (102) for separating a thin layer (103) and a thick layer (101) from silicon, where the component is made of a silicon substrate. An active zone (110) is formed by a thin layer portion (104) and connected to a set of distinct connection zones (115, 116). Another active zone (150) is formed by a thick layer portion (120) and connected to another set of distinct connection zones (126, 124). The thick layer portion is located directly above the thin layer portion.

Description

FIELD OF THE INVENTION The invention relates to the field of microelectronics. More particularly, it relates to electronic components made from totally depleted silicon-on-insulator substrate (or deserted complement), or FDSOI for "Fully Depleted Silicon on Insulator". BACKGROUND OF THE INVENTION In general, FDSOI type substrates comprise two layers of silicon, one of which is very thin, which are separated by a buried layer of oxide, generally called "box" for "buried oxide". . This type of substrate is used to produce components in the case where one seeks to take advantage of the fact that the thin layer of silicon makes it possible to reduce the power consumption. Under certain conditions, when certain applications implement relatively high intensities, it may be advantageous to use the thick layer of the FDSOI substrate to produce active zones, outside the zones where the active zones are made on the thin layer of the substrate. substrate. SUMMARY OF THE INVENTION One of the objectives of the invention is to increase the robustness of components made on FDSOI substrates with respect to electrostatic discharge phenomena. Another object of the invention is to increase the density of active areas within an FDSOI component. By "active areas" is meant regions of the substrate where currents of substantial intensity flow, as opposed to areas such as ground planes, which are mainly used to maintain a certain potential, and for which the currents observed are relatively weak. Thus, according to one aspect of the invention, there is provided an electronic component, made from a totally depleted silicon-on-insulator substrate (FDSOI), comprising an oxide layer separating two layers of silicon, namely a thin layer and a thick layer, comprising a first active zone, formed by a fraction of the thick layer, connected to at least two distinct connection zones, said fraction of the thick layer being constituted in line with said fraction of the thin layer.

Thus, according to the first aspect of the invention, it is possible to produce components in which active zones are superimposed, thus making it possible to combine on the same surface occupied on the substrate, several devices of the diode, transistor or other type.

According to other aspects of the invention, the upper face of the connection zones of the second deactivated zone may be located below the level of the upper face of the oxide layer separating the first and second active zones. an isolation trench can separate the connection areas of the second active area and the connection areas of the first active area. the connection areas of the second active zone may be located outside the connection zones of the first active zone. the two connection zones of the first active zone may have doping of the same polarity. the two connection zones of the second active zone may have doping of the same polarity, this polarity being the same as the polarity of the connection zones of the first active zone. the first active area may be covered with a gate structure having an oxide layer and a metal electrode. the second active zone can be separated from the rest of the thick layer by a buried insulation zone. Said insulating zone may be connected to a connection zone opening at the level of the oxide layer separating the first and second active zones. the connection areas of the second active area may be doped with opposite doping polarities. the connection areas of the first active area may be doped with opposite doping polarities. the connection areas of the first and second active regions which are arranged on the same side of the oxide layer separating the two active zones may have identical doping polarities. the zones of connection of the first and second active zones, which are arranged on the same side of the oxide layer separating the two active zones, may have different doping polarities.

Various configurations can be obtained, depending on the materials used can achieve components integrating various types of function, and can be declined and combined according to the desired applications. BRIEF DESCRIPTION OF THE FIGURES Certain aspects of the invention, and the associated advantages, will emerge from the description of various embodiments, with the aid of the appended figures in which: FIG. 1 is a schematic sectional view of a first embodiment embodiment, showing N MOS transistor structures.

Fig. 2 is an electrical diagram corresponding to Fig. 1. Fig. 3 is a schematic sectional view of a second embodiment showing P MOS transistor structures. Fig. 4 is an electrical diagram corresponding to Fig. 3. Fig. 5 is a schematic sectional view of a third embodiment, showing N-diode structures connected in parallel. Fig. 6 is an electrical diagram corresponding to Fig. 5. Fig. 7 is a schematic sectional view of a fourth embodiment showing diode P structures in parallel. Fig. 8 is an electrical diagram corresponding to Fig. 7. Fig. 9 is a schematic sectional view of a fifth embodiment, showing N-diode structures mounted antiparallel. Fig. 10 is an electrical diagram corresponding to Fig. 9. Fig. 11 is a schematic sectional view of a sixth embodiment, showing P-diode arrays mounted in antiparallel. Fig. 12 is a schematic sectional view of a seventh embodiment showing combined diode and MOS transistor structures. Figure 13 is an electrical diagram corresponding to Figure 12. Of course, the dimensions and positions of the various elements shown in the figures are given for illustrative purposes, and may differ from reality. DETAILED DESCRIPTION The various embodiments described in detail below have as common points that they are components made from a substrate 20 of the FDSOI type, in which two devices of the transistor or diode type are made for the purpose. one in the thick layer of the substrate, and for the other in the thin layer (TSi) of the same substrate, being arranged one above the other. Embodiment No. 1 The embodiment illustrated in FIG. 1 is made on an SOI substrate which comprises a thick layer 101, a buried insulating layer 102, also called a "box" for "buried oxide", and a thin layer of crystalline silicon 103. Above the upper face of the oxide layer 102, a first transistor 110 is formed. This transistor comprises a gate structure 111 composed of a metal electrode 112 and a layer This layer of oxide 113 rests on a zone 104 made in the thin layer of silicon 103. This layer 104 is slightly doped to form the channel of the transistor 110. In the illustrated example, this doping is of type P to realize an N-MOS transistor. In a conventional manner, the channel 104 is connected on each side to two doped zones with N-type doping, respectively to form the source 115 and the drain 116 of the transistor 110. The height of the zones 115 and 116 forming the source and the drain is such that their upper surface is at an intermediate level of the oxide layer, to insure the isolation of the channel 104.

Complementarily, outside the active zone formed by the transistor 110, the oxide layer 102 has been removed to give access to the bulk substrate forming the thick layer 101. Inside this layer 101, and immediately below the oxide layer 102 is a well 120 made by P type doping. This well 120 extends below the oxide layer 102, and protrudes laterally from the latter to be accessible from the openings made in the oxide layer 102. This well 120 is isolated from the rest of the substrate 101, by a deep well 122, made by an N-type doping, and which includes the well 120.

The well 120 is intended to accommodate the channel of the buried transistor, and is therefore connected to two connection areas, forming the source 124 and the drain 126 of the buried transistor. The source and the drain are produced by epitaxy and doping as a function of the type of transistors desired, and therefore of type N for the example of FIG. 1.

The heights of the source zone 124 and drain 126 of the buried transistor are controlled during the epitaxial process to prevent the source and the drain of the buried transistor from coming into contact with the source and the drain of the transistor formed above the transistor. Thus, the epitaxy, performed to realize the source 124 and the drain 126 of the buried transistor, is stopped before reaching the level of the upper face of the oxide layer 102.

The use of STI type trenches is illustrated in FIG. 1 to separate other connection points from the buried transistor. Thus, the deep well 122 is connected to a connection zone 128 through a zone 129 of similar doping, N-Well type. The connection zone 128 is formed at the same time as the production of the source 124 and drain 126 of the buried transistor. An isolation trench 130 is thus produced between the source 124 and the connection zone 128 to the isolation box 122, to enable the independent controls of the transistor and its isolation zone. In the same way, an isolation trench 136 is formed between the drain 126 of the buried transistor and the connection zone 138, made in a doping of the same polarity as the well 120, in order to control the potential of the body (or "body" 120), that is to say the area of the substrate where the channel of the buried transistor is formed. Of course, other isolation trenches 140 may be provided to separate the pair of transistors 110, 150 from adjacent regions. Thus, and as illustrated in FIG. 2, the upper transistor 110 operates in a conventional manner for an N-MOS transistor of the FDSOI type. Note that in the illustrated configuration, the buried transistor 150 has a gate which is formed by the combination of the oxide layer 102 of the substrate, associated with an electrode formed by the body 103 of the upper transistor. This type of assembly can have various applications and interest and in particular in the field of the treatment of electrostatic discharges, with a triggering of the buried transistor, capable of draining a high intensity current, by turning on the upper transistor. Embodiment No. 2 The embodiment illustrated in FIG. 3 is similar to that of FIG. 1, of which it differs essentially in that the connected transistors are of the P 5 MOS type. SOI substrate is thus found which comprises a thick layer 201, and a Box 202 layer, and a thin layer of epitaxial silicon 203. Above the upper face of Box 202, is the upper transistor 210. This transistor 210 comprises an active zone formed by a slightly doped fraction 204 of the thin layer of the substrate, associated with two zones having a P-type doping, forming the source 215 and the drain 216 of the transistor 210. This active zone, and more precisely the layer 204 of silicon forming the channel of the transistor is covered with a gate structure 211 formed of an oxide layer 213, itself covered with a metal electrode 212. As for the preceding example, the height of the zones 215, 216 forming the source and the drain is sufficient to cover the total height of the channel 203. As for Example 1, outside the active zone formed by the transistor 210, the oxide 202 has been eliminated ee, to give access to the substrate forming the thick layer 201. Inside this layer, and more precisely below the oxide layer 202 of the substrate, there is a then 220, made by an N-type doping. then 220 is plumb with the oxide layer 202, and extends laterally to be accessible from the openings made in the oxide layer 202. Under this well 220 is formed a deep well of similar doping . The well 220 is connected to two connection areas forming the source 224 and the drain 226. The source and the drain are made by epitaxy and P-type doping, to produce a P-type MOS transistor. The height of the source zones forming the source 224 and the drain 226 are controlled during the epitaxial process to avoid creating a direct connection with the source 215 and the drain 216 of the upper transistor.

As for the previous example, isolation trenches or STIs can also be set up near the source and drain epitaxial zones to prevent such a connection. Another isolation trench 227 is provided to isolate the source 224 of the buried transistor from a connection point 228 for picking up the potential of the well 220. Similarly, an isolation trench 236 may be provided between the source 226. of the buried transistor and a connection point 238 for controlling the potential of the substrate 201.

Thus, and as illustrated in FIG. 4, the upper transistor 210 operates in a conventional manner for a POS transistor MOS of the FDSOI type. As for Example 1, the buried transistor 250 has a gate which is formed by the combination of the oxide layer 202 of the substrate associated with the electrode which is formed by the body 204 of the upper transistor.

Embodiment No. 3 The embodiment illustrated in FIG. 5 is similar to that of FIGS. 1 and 3, of which it essentially differs by the different dopings used to form the upper and buried active zones, in order to create junctions. PN and hence diode assemblies. Thus, there is thus found an SOI substrate which comprises a thick layer 301, a layer of BOX 302 and a thin layer of epitaxial silicon 303. Above the upper face of the BOX 302, is the active zone 310. active is formed by a fraction 304 of the thin layer of the substrate, associated with two zones having doping of opposite polarity, and more precisely an N-type doping zone to form the cathode 316, and a P-type doping to form the anode 315, and thus form a diode. According to the doping of the thin layer of the FDSOI substrate, the junction P N of the diode 310 is therefore close to the anode or the cathode.

In the form shown, the thin layer of the substrate receives a gate structure 311, formed of an oxide layer 313, itself covered with a metal electrode 312. The presence of this gate 311 makes it possible to define a controlled diode by the grid. However, in certain embodiments, this gate structure may be absent, so as to produce a conventional diode. As for the preceding examples, outside the active zone formed by the diode 310, the oxide layer 302 has been removed to give access to the substrate forming the thick layer 301. Inside this layer, and in particular under the oxide layer 302 of the substrate, there is a well 320, made by a P-type doping. This well 320 is located vertically above the oxide layer 302 and extends laterally to be accessible. from the openings made in the oxide layer 302.

Under this well 320 is formed a deep well of opposite doping to ensure the isolation of the well 320 relative to the rest of the substrate. The well 320 is connected to two connection zones forming the anode 324 and the cathode 326 of the buried diode 350. These two zones are produced by epitaxy using different dopings, and more precisely of the P type for the anode and N for the cathode, in order to define an N-diode. The deep well 322 makes it possible to isolate the well 320 from the diode from the remainder of the substrate.

As for the preceding examples, the height of the zones forming the cathodes 326, and the anode 324 are controlled during the epitaxial processes, to avoid coming to create a direct connection with the anode 315 and the cathode of the diode 310. These provisions being particularly used when it is desired to make independent connections of the two diodes. However, in the case where it is desired to mount the two diodes in parallel, it is possible to realize the epitaxies of the anode and the cathode of buried diodes to ensure direct contact with the anode and the cathode respectively. 315, 316 of the upper diode. It is also possible to make a common contact (or "shared contact"), which falls astride the thin layer of silicon, and on the substrate.

It is also possible, as in the previous examples, to make isolation type trenches or STI, to physically separate cathodes 316, 326 and anodes 315, 324 from the two diodes.

Another trench 327 is made to isolate the anode 324 from the buried diode with respect to the connection point 328 making it possible to take the potential of the deep well 320. Similarly, an isolation trench 336 may be provided between the cathode 326 of the the buried diode and the rest of the component.

Thus, and as illustrated in FIG. 6, the upper diode and the lower diode can be connected in parallel since they are, depending on the thickness of the oxide layer 302, an electrostatic type interaction can be observed, thus modifying the threshold voltage of one of the diodes when the other diode is conductive.

In practice, the presence of two diodes of different design and construction makes it possible to benefit from two diodes with distinct properties, in particular in terms of dynamics and supported currents.

A mode of operation of these two diodes can implement photonic coupling phenomena between the two diodes. Indeed, the conduction of one of the two diodes causes the recombination of carriers, the emission of - photons. These photons can interfere on the other diode, in particular by modifying its threshold voltage. This construction has a particular advantage in the field of electrostatic discharge treatment.

Embodiment No. 4 Example 4 illustrated in FIGS. 7 and 8 is analogous to example 3 with the distinction that the diodes produced are of the P type. In this case, the upper diode 410 is identical to the upper diode. of Example 3. In contrast, the buried diode 450 is formed by the formation of a Well N type well 420, positioning the PN junction buried diode near the anode 424. Just as for the example 2, implementing a P MOS, the potential of the substrate can be controlled by the connection zone 428 of similar dopings.

Embodiment 5 The example 5 illustrated in FIGS. 9 and 10 is similar to example 3, with the only difference that the anode 515 and the cathode 516 of the upper diode are inverted, so that the upper diode 510 is in anti-parallel of the diode buried 550.

In this example of anti-parallel diodes, the presence of isolation trenches may be preferred to separate the anode and the cathode from the upper and lower diodes. More precisely, and as illustrated in FIG. 9, the isolation trench 562 makes it possible to prevent any unexpected connection between the anode 515 of the upper diode 510 and the cathode 526 of the buried diode 550, in order to avoid that a contact between these two zones does not remove the PN junction of one or other of the diodes. A trench 560 is provided in the same way, to separate the cathode 516 from the upper diode 550, and the anode 524 from the buried diode. Thus, as shown in FIG. 10, the two buried and upper diodes are arranged. in anti-parallel, which may have advantages in some applications, especially for mass connections.

Embodiment No. 6 The example illustrated in FIG. 11 is deduced from example 4, from which it differs only by the inverted positioning of the anode and the cathode of the upper diode. As for example 5, the presence of isolation trenches 10 will be favored to prevent any inadvertent connection between anode and cathode of the two diodes. The equivalent diagram of the two diodes thus formed corresponds to that of FIG. 10. Embodiment No. 7 This example, illustrated in FIGS. 12 and 13, is derived from the structure described in FIG. that the buried active area forms a diode. More precisely, the substrate comprises, above the oxide layer 702, an active zone 710, forming a structure of N-MOS type transistors. This active area comprises a layer 704 forming a fraction of the thin layer of the substrate, which is connected to two zones formed by epitaxy and constituting the source 715 and the drain 716 of the transistor 710. The layer 704 forming the channel of the transistor receives a gate structure 711, composed of an oxide layer 713 and a metal electrode 712. Below the oxide layer 720, the substrate has a doping box P, which is separated from the rest of the substrate by a deepwell 722. The well 720 is connected to the upper face of the component by a cathode 724, anode 726, made with distinct dopings, so as to form a PN junction thus defining the buried diode 750. 2 9 8 7 6 The anode 726 is separated from the drain 716 of the upper transistor, which is made in opposite doping, via an isolation trench. 762. This trench thus makes it possible to avoid the deletion of the PN junction of the diode by unintentional contact of the anode 726 and the cathode 716. The deep well 722 is connected to the outside of the component by a zone of contact 728, formed by a similar doping epitaxy.

The equivalent diagram of such a component is illustrated in FIG. 13. It can be seen that the MOS transistor 710 formed on the upper part has its channel which rests on the channel of the buried diode, with which it interacts electrostatically or even photonically. . Such a component may exhibit a particular behavior during the conduction of the buried diode, which modifies the threshold voltage of the upper transistor 710. Such a component may therefore have a particular application in the circuits of "keep off" or tripping in the case of the treatment of electrostatic discharges. Of course, the various embodiments can be combined or declined as much as possible, and remain in the spirit of the invention. Although described more specifically for SOI substrates based on silicon, the invention can be implemented with other semiconductors. From the foregoing, it will be apparent that the components according to the different embodiments have particular advantages of combining a plurality of devices into an extremely small area.

Claims (4)

CLAIMS1 / Microelectronic component, made from a completely depleted silicon-on-insulator substrate (FDSOI), comprising an oxide layer (102) separating two silicon layers, namely a thin layer (103) and a layer thick film (101), having a first active area (110), formed by a fraction (104) of the thin layer connected to at least two distinct connection areas (115, 116), and having a second active area (150), formed by a fraction (120) of the thick layer (101), connected to at least two distinct connection areas (126, 124), said fraction (120) of the thick layer being located in line with said fraction ( 104) of the thin layer. 2 / A component according to claim 1 wherein the upper face of the connection regions (126, 124) of the second active zone is located below the level of the upper face of the oxide layer (102) separating the first (110) and second (150) active areas. 3 / A component according to claim 1, wherein an isolation trench (560, 562) separates the connection areas (526, 524) from the second active zone and the connection zones (516, 515) from the first zone active. 4 / A component according to claim 1, wherein the connection areas (126, 124) of the second active zone are located outside the connection areas (115, 116) of the first active zone. 5. The component according to claim 1, wherein the two connection zones (115, 116) of the first active zone have doping of the same polarity. 6 / A component according to claim 1, wherein the two zones (126, 124) of connection of the second active zone have doping of the same polarity, said polarity being the same as the polarity of the connection zones of the first active zone. The component of claim 1, wherein the first active area is covered with a gate structure (111) having an oxide layer (113) and a metal electrode (112). 8 / component according to claim 1, the second active zone (120) is separated from the rest of the thick layer by a buried insulation zone (122). 9 / A component according to claim 8, wherein said isolation zone (122) is connected to a connection zone (128) opening at the oxide layer (102) separating the first and second active zones. 10 / A component according to claim 1, wherein the connection areas (324, 326) of the second active zone are doped with opposite doping polarities. 11 / Component according to claim 1, the connection zones (315, 315) of the first active zone are doped with polarities of opposite doping. 12. The component according to claim 1, wherein the connection zones (316, 336, 315, 324) of the first and second active zones which are arranged on the same side of the oxide layer separating the two active zones, have identical doping polarities. 13. The component of claim 1, wherein the connection areas 515, 526; 516, 524) first and second active areas which are arranged on the same side of the oxide layer separating the two active areas, have different doping polarities.